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SY89228U

Status: In Production

Features:

  • Accepts a high-speed input and provides a precision ÷3 and ÷5 sub-rate, LVPECL output
  • Prevents oscillations when input is invalid
  • DC-to >1.0GHz throughput
  • <1500ps Propagation Delay (In-to-Q)
  • <270ps Rise/Fall times
  • <1psRMS random jitter
  • <1psRMS cycle-to-cycle jitter
  • <10psPP total jitter (clock)
  • <0.7psRMS MUX crosstalk induced jitter
  • Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
  • Wide input voltage range VCC to GND
  • 800mV LVPECL output
  • 46% to 54% Duty Cycle(÷ 3)
  • 47% to 53% Duty Cycle(÷ 5)
  • 2.5V ±5% or 3.3V ±10% supply voltage
  • -40°C to +85°C industrial temperature range
  • Available in 16-pin (3mm x 3mm) QFN package
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Device Overview

Summary

The SY89228U is a precision, low jitter 1GHz ÷3, ÷5 clock divider with an LVPECL output. A unique Fail-Safe Input (FSI) protection prevents metastable output conditions when the input clock voltage swing drops significantly below 100mV or input is removed.The differential input includes Micrel's unique, 3-pin internal termination architecture that allows the input to interface to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with fast rise/fall times guaranteed to be less than 270ps.The SY89228U operates from a 2.5V ±5% or 3.3V ±10% supply and is guaranteed over the full industrial temperature range of -40°C to +85°C. The SY89228U is part of Micrel's high-speed, Precision Edge® product line.

Additional Features
    • Accepts a high-speed input and provides a precision ÷3 and ÷5 sub-rate, LVPECL output
    • Fail-Safe Input
      • Prevents oscillations when input is invalid
    • Guaranteed AC performance over temperature and supply voltage:
      • DC-to >1.0GHz throughput
      • <1500ps Propagation Delay (In-to-Q)
      • <270ps Rise/Fall times
    • Ultra-low jitter design:
      • <1psRMS random jitter
    • <1psRMS cycle-to-cycle jitter
    • <10psPP total jitter (clock)
    • <0.7psRMS MUX crosstalk induced jitter
    • Unique patented internal termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS)
    • Wide input voltage range VCC to GND
    • 800mV LVPECL output
    • 46% to 54% Duty Cycle(÷ 3)
    • 47% to 53% Duty Cycle(÷ 5)
    • 2.5V ±5% or 3.3V ±10% supply voltage
    • -40°C to +85°C industrial temperature range
    • Available in 16-pin (3mm x 3mm) QFN package
Parametrics
Name
Value
Product Type
Divider
Description
÷3, ÷5;1 Output
Input
ANY
Output
LVPECL
Supply Voltage
2.5/3.3V
Max Freq (GHz)
1
Max Prop Delay (ps)
1500
Icc (mA)
40
Max Within Device Skew (ps)
450
OE
False
RPE
False
FSI
True
Input Mux
False
Input EQ
False
Output Type
LVPECL

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