Microchip Technology Inc
product primary image

SY87701V

Status: In Production

Features:

  • 3.3V and 5V power supply options
  • Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream, clock generation from 32Mbps to 1.25Gbps
  • Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, Fibre Channel and Gigabit Ethernet, as well as proprietary applications
  • Two on-chip PLLs:one for clock generation and another for clock recovery
  • Selectable reference frequencies
  • Differential PECL high-speed serial I/O
  • Line receiver input: no external buffering needed
  • Link fault indication
  • 100k ECL compatible I/O
  • Available in 32-pin ePad-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs)
View More
Overview
Documents
Development Environment
RoHS Information
Buy Now

Device Overview

Summary

Use lower-power SY87701AL for 3.3V systems The SY87701V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.25Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87701V also includes a link fault detection circuit.

Additional Features
    • 3.3V and 5V power supply options
    • Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream, clock generation from 32Mbps to 1.25Gbps
    • Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, Fibre Channel and Gigabit Ethernet, as well as proprietary applications
    • Two on-chip PLLs:one for clock generation and another for clock recovery
    • Selectable reference frequencies
    • Differential PECL high-speed serial I/O
    • Line receiver input: no external buffering needed
    • Link fault indication
    • 100k ECL compatible I/O
    • Available in 32-pin ePad-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs)
Parametrics
Name
Value
Part Type
Clock and Data Recovery
Data Rate Capability
32-1250Mbps
Power Supply (V)
3.3, 5.0
Data Output Type
PECL

Documents

Jump to:

Data Sheet

11/11/2015
142KB

Development tools data is currently unavailable.


Rohs data is currently unavailable.

Buy

Grid
View
Table
View
Filter:
Apply
Clear
Product
Leads
Package Type
Temp Range
Packing Media
5K Pricing
Buy