The SY87700V is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 175Mbps NRZ. The device is ideally suited for SONET/SDH/ATM applications and other high-speed data transmission systems.
Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference.
The SY87700V also includes a link fault detection circuit.
3.3V and 5V power supply options
Clock and data recovery from 32Mbps up to 175Mbps NRZ data stream, clock generation from 32Mbps to 175Mbps
Two on-chip PLLs: one for clock generation and another for clock recovery
Selectable reference frequencies
Differential PECL high-speed serial I/O
Line receiver input: no external buffering needed
Link fault indication
100k ECL compatible I/O
Complies with Bellcore, ITU/CCITT and ANSI specifications such as OC-1, OC-3, FDDI, Fast Ethernet, as well as proprietary applications
Available in 32-pin ePad-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but not recommended for new designs)