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SY100H602

9-bit Latched TTL-to-ECL

Status: Not Recommended for new designs

Features:

  • 9-bit ideal for byte-parity applications
  • Flow-through configuration
  • Extra TTL and ECL power/ground pins to minimize switching noise
  • Dual supply
  • 3.5ns max. D to Q
  • PNP TTL inputs for low loading
  • Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx)
  • Fully compatible with MC10H/100H602
  • Available in 28-pin PLCC package
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Device Overview

Summary

The SY10/100H602 are 9-bit, dual supply TTL-to-ECL translators with latches. Devices in the Micrel 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance.The H602 features D-type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post-latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level.The 10H version is compatible with MECL 10KH ECL logic levels. The 100H version is compatible with 100K levels.

Additional Features
    • 9-bit ideal for byte-parity applications
    • Flow-through configuration
    • Extra TTL and ECL power/ground pins to minimize switching noise
    • Dual supply
    • 3.5ns max. D to Q
    • PNP TTL inputs for low loading
    • Choice of ECL compatibility: MECL 10KH (10Hxxx) or 100K (100Hxxx)
    • Fully compatible with MC10H/100H602
    • Available in 28-pin PLCC package
Parametrics
Name
Value
Input
ANY
Supply Voltage
5V
Max Freq (GHz)
2
Icc (mA)
75
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Output Type
LVDS
Output Voltage
2.5V

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