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SY100EL14V

Status: In Production

Features:

  • 3.3V and 5V power supply options
  • 70fsRMS typical additive phase jitter
  • Typical 30ps output-to-output skew
  • Max. 50ps output-to-output skew
  • Synchronous enable/disable
  • Multiplexed clock input
  • 75KΩ internal input pull-down resistors
  • Available in 20-pin SOIC package
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Overview
Documents
Development Environment
RoHS Information
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Device Overview

Summary

The SY100EL14V is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The EL14V is suitable for operation in systems operating from 3.3V to 5.0V supplies. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor.

The VBBoutput is designed to act as the switching reference for the input of the EL14V under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.The EL14V features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2.

Additional Features
    • 3.3V and 5V power supply options
    • 70fsRMS typical additive phase jitter
    • Typical 30ps output-to-output skew
    • Max. 50ps output-to-output skew
    • Synchronous enable/disable
    • Multiplexed clock input
    • 75KΩ internal input pull-down resistors
    • Available in 20-pin SOIC package
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Description
2:5
Input
ECL/PECL
Output
PECL
Supply Voltage
3.3/5
Max Freq (GHz)
0.75
Max Prop Delay (ps)
880
Icc (mA)
32
Max Within Device Skew (ps)
50
OE
True
RPE
False
FSI
False
Input Mux
True
Input EQ
False
Output Type
PECL

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RoHS Information

Part Number
Device Weight (g)
Shipping Weight (Kg)
Lead Count
Package Type
Package Width
Solder Composition
JEDEC Indicator
RoHS
China EFUP
SY100EL14VZG-TR
0.540800
1.461700
20
SOIC
.300in
NiPdAu
e4
SY100EL14VZG
0.540800
1.086316
20
SOIC
.300in
NiPdAu
e4
To see a complete listing of RoHS data for this device, please Click here
Shipping Weight = Device Weight + Packing Material weight. Please contact sales office if device weight is not available.

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