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PL671-25

Status: In Production

Features:

  • Max. propagation delay of 3.7ns
  • IEE min. of -37mA
  • TTL outputs
  • Extended supply voltage option: VEE = -4.2V to -5.5V
  • 25% faster than National''s 325
  • Differential inputs with built-in offset
  • Voltage and temperature compensation for improved noise immunity
  • VBB output for single-ended use
  • Internal 75KΩ input pull-down resistors
  • Function and pinout compatible with Fairchild F100K
  • Available in 28-pin PLCC package
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Device Overview

Summary

The SY100S325 are hex translators for converting 100K ECL logic levels to TTL logic levels. Inputs can be used as inverting, non-inverting or differential receivers.

An internal reference voltage generator provides VBB for single-ended operation or for use in Schmitt trigger applications. All inputs have 75KΩ pull-down resistors. The outputs will go LOW when the inputs are either open or have the same potential.

When used in single-ended operation, the apparent input threshold of the true inputs is 20mV to 40mV higher (positive) than the threshold of the complementary inputs. The VTTL and VEE power may be applied in either order.

Additional Features
    • Max. propagation delay of 3.7ns
    • IEE min. of -37mA
    • TTL outputs
    • Extended supply voltage option: VEE = -4.2V to -5.5V
    • 25% faster than National's 325
    • Differential inputs with built-in offset
    • Voltage and temperature compensation for improved noise immunity
    • VBB output for single-ended use
    • Internal 75KΩ input pull-down resistors
    • Function and pinout compatible with Fairchild F100K
    • Available in 28-pin PLCC package
Parametrics
Name
Value
Product Type
Clock Conditioning
Description
EMI Reduction
PLLs
1
Input Frequency (MHz) Crystal
10-40
Input Frequency (MHz) Reference
1-200
Output Frequency (MHz)
1-200
# of Outputs
2
Voltage
2.5 - 3.3
PDB
True
OE
False
FSEL
False
CSEL
True
CLK
False
Output Logic
CMOS
Ultra Low Power
False
Output Frequency Min. (MHz)
1
Output Frequency Max. (MHz)
200

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