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MDB1900ZB

Status: In Production

Features:

  • Supports zero delay (0ps) buffer mode for 100MHz and 133MHz clock frequencies.
  • External feedback path for true zero delay operations
  • Zero delay (PLL) mode can filter jitter in incoming clock
  • Selectable PLL bandwidth for PLL mode
  • Supports fanout buffer mode for clock frequencies between 0MHz and 250MHz
  • Differential input reference with HCSL logic (0V ~ 0.7V)
  • Nineteen differential HCSL-compatible clock output pairs
  • Eight dedicated OE# pins to control their assigned output. Glitch free assertion/de-assertion.
  • Spread spectrum modulation tolerant for EMI reduction
  • SMBus interface for controlling output properties (enable/disable and delay tuning)
  • Disabled outputs in power-down mode for maximum power savings
  • Nine selectable SMBus addresses so multiple devices can share the same SMBus
  • 3.3V or 2.5V operation
  • Commercial temperature range (0°C to +70°C)
  • 72-pin 10mm × 10mm QFN package
  • GREEN, RoHS, and PFOS compliant
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Overview
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Device Overview

Summary

The MDB1900ZB is a true zero delay buffer with fully integrated high-performance, low-power, and low phase noise programmable PLL.The MDB1900ZB is capable of distributing the reference clocks for PCIe (Gen1/Gen2/Gen3), SATA, ESI, SAS, SMI, and Intel® Quickpath Interconnect (QPI). The MDB1900ZB works in conjunction with a CK410B+, CK509B, or CK420BQ clock synthesizer to provide reference clocks to multiple agents.The MDB1900ZB is designed for Intel’s DB1900Z specification. The Intel part designation for the MDB1900ZB is identified as G20746-002.

Additional Features
    • Supports zero delay (0ps) buffer mode for 100MHz and 133MHz clock frequencies.
    • External feedback path for true zero delay operations
    • Zero delay (PLL) mode can filter jitter in incoming clock
    • Selectable PLL bandwidth for PLL mode
    • Supports fanout buffer mode for clock frequencies between 0MHz and 250MHz
    • Differential input reference with HCSL logic (0V ~ 0.7V)
    • Nineteen differential HCSL-compatible clock output pairs
    • Eight dedicated OE# pins to control their assigned output. Glitch free assertion/de-assertion.
    • Spread spectrum modulation tolerant for EMI reduction
    • SMBus interface for controlling output properties (enable/disable and delay tuning)
    • Disabled outputs in power-down mode for maximum power savings
    • Nine selectable SMBus addresses so multiple devices can share the same SMBus
    • 3.3V or 2.5V operation
    • Commercial temperature range (0°C to +70°C)
    • 72-pin 10mm × 10mm QFN package
    • GREEN, RoHS, and PFOS compliant
Parametrics
Name
Value
Product Type
Fanout & Buffer and Drivers
Input
HCSL
Supply Voltage
2.5/3.3
Max Within Device Skew (ps)
35
OE
False
RPE
False
FSI
False
Input Mux
False
Input EQ
False
Voltage (V)
2.5V, 3.3V
Output Type
HCSL
Input (MHz)
100, 133
Number Of Outputs
19

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