Interleaved Power Factor Correction
Recording Date: 08/17/2009
Duration: 14 min
This Web Seminar will discuss the Interleaved Power Factor Correction (IPFC) reference design. This reference design provides an easy method to evaluate the power, and features of SMPS dsPIC® Digital Signal Controllers for an IPFC application.
Presenter: Jorge Zambada, Applications Engineer, DSC Division
Jorge joined Microchip in 2004 as an Applicatios Engineer for the Digital Signal Controller Division, and has been working in the area of Motor Control and embedded systems since 2001. Before joining Microchip, he worked at Motorola/Freescale as an Applications Engineer focused on Motor Control applications. Jorge obtained a Bachelors Degree in Electronics Systems Engineering from the Monterrey Institute of Technology, ITESM, in Guadalajara, Mexico.
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