Re:12F675 EEPROM Wear leveling
That's why you *MUST* add a counter - if you don't have something that increments sequentially every time you need to store your power loss data, you cannot track the wear so cant implement wear levelling.
The strategy above basically writes a data set to the current block 256 times then moves on to the next block. As the high byte of the counter is only updated at 1/256 of the rate of the other data, it does not wear out quickly and you can use it to locate which block is currently active. The low byte of the counter is kept in the current block.
You could have 16 x 7 byte blocks, one byte of each being lost to the counter, giving you 6 bytes of 16 x endurance user data storage for a total cost of 113 bytes of EEPROM, or if you went to a 5 bit block number, you could have 32 x 3 byte blocks giving you 2 bytes of
32 x endurance user data storage for a total cost of 97 bytes of EEPROM.
The 5 bit block number 32 x endurance, would extend the worst case extended temperature range endurance of 10K writes/byte to 320K writes. If you can guarantee that you don't write a block more often than once every 5 seconds, that gives you over thee years endurance even if the power fails every 5 seconds 24/7. When you run out of theoretical endurance, or maybe when you start getting write errors, program three "EEPROM Fail" bytes with 0xA5 that were originally programmed as 0x5A and are never otherwise written. If any of the bits in any of those bytes have been flipped, you know you cannot trust the whole EEPROM.
Finally, don't store anything critical at location 0! It is advisable to always clear EEADR after use so a rogue write caused by something crashing the PIC doesn't smash anything important.
If you are using external EEPROM ,you need to make sure that your data blocks are aligned on write/erase page boundaries. Not a problem for the internal EEPROM as it has true byte access.