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SPI receive bug "kinda" in errata for the 24FJ256GA110

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dlc@frii.com
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2010/11/04 09:47:30 (permalink)
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SPI receive bug "kinda" in errata for the 24FJ256GA110

I've found a bug in the 24FJ128GA106 part (what I'm using) that is in the SPI module.  I've found that when the following code is run, I'll be one SPIBUF receive value off (I'll get one too many).  I'll tell you why in a moment.

    while (SPI2STATbits.SPITBF) ;            // Wait for it to be safe before transmitting
    SPI2BUF = wordOut;
    while (!SPI2STATbits.SPIRBF) ;            // per Section 23 SDI details
    *wordIn = SPI2BUF;                        // This is what we got back
 


I should get 24 words (16 bit mode) with a flag on the last word and I get 25 words before the flag.  Hmm.  A suspicious coworker suggested I put a delay in after the SPIRBF check.  Wow, now I get the right number of transfers!  His thought, the shift register hasn't yet been moved to SPI1BUF.

I checked errata and found one for SPI on this part that says if you have enhanced buffer mode disabled and CKE = 1 then the RBF bit is set 1/2 clock cycle early!  I am in mode 00 (CKE and CKP = 0).  I tried the errata fix, which has the code look for the SCK line to go low but because I use mode 00 as my SPI mode it doesn't work.  What DID work was the following code, which I hate, but it solves the problem.

    while (SPI2STATbits.SPITBF) ;            // Wait for it to be safe before transmitting
    SPI2BUF = wordOut;
    while (!SPI2STATbits.SPIRBF) ;            // per Section 23 SDI details
    while(i++ < 3);                            // Errata, RBF is set 1/2 SCK clock early
    *wordIn = SPI2BUF;                        // This is what we got back


A quick count of the instruction cycles showed me that I needed this loop to use about 16 instructions before it would work, which coincidentally came to 1us, which matched my clock rate of 1MHz.

So if you appear to be getting delayed data in your SPI loop, look to this above fix to solve the RBF and IF flags being set 1/2 clock cycle early, which causes you to pull stale data from the SPIxBUF register.

have fun,
DLC

So,
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6 Replies Related Threads

    DarioG
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/04 15:41:53 (permalink)
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    Thank you Dennis, I'm using that part with the TCP/IP stack and some code of mine, without troubles: IIRC, Microchip did implement some checks/workarounf in the code...

    GENOVA :D :D ! GODO
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    dlc@frii.com
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/05 10:00:18 (permalink)
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    DarioG

    Thank you Dennis, I'm using that part with the TCP/IP stack and some code of mine, without troubles: IIRC, Microchip did implement some checks/workarounf in the code...


    Hey Dario,

      I get enough info from this board I thought that I'd give some back.  The MC errata gives a workaround for one of the SPI modes, a pretty common one, but it doesn't work with the other modes.  If you are using the 8 byte enhanced FIFO SPI modes then this isn't a problem since the hardware knows all and sets it up properly.  That mode would have complicated my more "real time" needs so I left it in the old-fashioned single transaction mode.  As it turns out the extra 1.5us latency my solution adds is less than 10% of the hardware latency of 16us between 16 bit transfers anyway (according to my scope) so it is a "no big deal" kind of thing and I feel better. :-)

    Have fun,
    DLC
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    DarioG
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/05 11:05:55 (permalink)
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    I see,
    I'm not exacly sure which modes are used with the ENC, since I took the stack "as is" and was good enough.

    But will check Smile

    GENOVA :D :D ! GODO
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    dlc@frii.com
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/10 08:11:40 (permalink)
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    DarioG

    I see,
    I'm not exacly sure which modes are used with the ENC, since I took the stack "as is" and was good enough.

    But will check Smile


    My guess is that they are either using the advanced buffered mode for performance or mode 01 (or is the 10?) and know of the silicon bug.  They'll be going for the best transfer rate that they can.  How well does the ENCJ<mumble> chip and network setup work?  I worked earlier with the 18F series and their demo web server and found that rather painful in how difficult it was to encode web pages and interactive data exchange.  Has that improved?  I'm pretty sure that the 24F parts make this easier with the large increase in RAM and FLASH available, but I'm curious.  I'm beginning to really like the 16 bit parts price/performance.

    have fun,
    DLC
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    DarioG
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/10 15:20:31 (permalink)
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    Yeah, me converting to 24 as well Smile

    I've not done many TCP/IP apps so far, but they were working good enough; and so they seem the 24F.

    Well, the pages-ajax etc side has remained more or less the same: there have been some improvements in the file system (MPFS2 or even FAT is in use now, not sure if you already tested it) and Ajax (javascript) is used for real-time updates in the pages - and not is not too difficult to implement.

    GENOVA :D :D ! GODO
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    dlc@frii.com
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    Re:SPI receive bug "kinda" in errata for the 24FJ256GA110 2010/11/11 10:16:41 (permalink)
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    DarioG

    Yeah, me converting to 24 as well Smile

    I've not done many TCP/IP apps so far, but they were working good enough; and so they seem the 24F.

    Well, the pages-ajax etc side has remained more or less the same: there have been some improvements in the file system (MPFS2 or even FAT is in use now, not sure if you already tested it) and Ajax (javascript) is used for real-time updates in the pages - and not is not too difficult to implement.


    Sounds similar.  Cool, I'll keep it in mind if and when such a project pops up!

    Thanks,
    DLC
    #7
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