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SPI reliability

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Tom Myers
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2009/06/23 06:53:49 (permalink)
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SPI reliability

Hi,

I am using both SPI ports on the dsPIC33FJ128MC804 and I am experiencing some reliability issues. Firstly, devices on both SPI ports receive and process commands most of the time - I have closely analysed timing of the CLK, SDI and CS lines to make sure they meet the manufacturers specifications for the devices I am using along with the maximum allowable clock frequency.

The circuit I am working on is based around Explorer 16 with the break-out pictail to some devices on breadbread and veroboard - I am aware of the potential issues surrounding this with regard to high clock frequencies, however my SPI clock is in the 10's KHz range. I am using an external 8MHz oscillator with no PLL and programming using ICD2 in debug mode, in the C30 compiler.
 
I am not using resistors on any of the lines! I thought SPI didn't require this? But since I have seen this post, which suggests otherwise?
 
http://www.microchip.com/forums/tm.aspx?m=148739
 
Could this be my demise?

Here are some things I have tried when the devices have not successfully received or processed the SPI commands:

> Implementing a processor reset (F6) from within MPLAB
> Turning power on and off again (although I have not implemented clock switching)
> Placing scope probes on the CLK and SDI lines helps!!!?? [8|]

Any thoughts and comments greatly accepted!

Regards,
Tom

post edited by Tom Myers - 2009/06/23 07:19:02
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18 Replies Related Threads

    danish.ali
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    RE: SPI reliability 2009/06/23 07:41:49 (permalink)
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    It doesn't matter what clock speed you are using.
    What matters is what speed the devices you use are capable of running at, because glitches on this time-scale will upset operation.

    Things to look at:
    Power-supply-decoupling around your SPI device(s) - this must be very close with short wires.
    Matching of the wires used to carry the SPI signals. Add a series resistor (e.g. 10 k) at the sending end.
    Ground-bounce. You have not told us what those SPI devices are. Do they / can they draw a lot of current? Do they have a lot of outputs, which might all switch simultaneously? If they can, then you must get the decoupling even better than the "normal" 0.1 uF as-close-as-possible-to-the-chip.

    I am not a fan of solderless-breadboard, but veroboard/stripboard can work with careful layout and short wires.

    I did not notice what your SPI devices are. Might they have (as part of their normal operation) a "dead" period where they cannot execute new commands, and can only respond to "polling" as to if the last command has completed? (EEPROM memory can behave like this).

    Regards,
    Danish
    #2
    Tom Myers
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    RE: SPI reliability 2009/06/23 07:55:01 (permalink)
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    Hi Danish,
     
     
    Matching of the wires used to carry the SPI signals. Add a series resistor (e.g. 10 k) at the sending end.
    Ground-bounce. You have not told us what those SPI devices are. Do they / can they draw a lot of current? Do they have a lot of outputs, which might all switch simultaneously? If they can, then you must get the decoupling even better than the "normal" 0.1 uF as-close-as-possible-to-the-chip.

     
    My signal wires are pretty well matched. I will try the series resistor technique.
     
    Ground bounce is not so much an issue, since the SPI devices PGA, DDS and digital POT's with little energy consumption or switching.
     

    I did not notice what your SPI devices are. Might they have (as part of their normal operation) a "dead" period where they cannot execute new commands, and can only respond to "polling" as to if the last command has completed? (EEPROM memory can behave like this).


     
    This is an interesting idea. I am not aware of any period where these devices are unavailable to receive new commands, they are all pretty simple devices that do not really get tied up doing things, as I said PGA, POT and a DDS.
     
    Regards,
    Tom
    #3
    danish.ali
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    RE: SPI reliability 2009/06/23 08:14:43 (permalink)
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    Hi Tom,

    PGA = programmable gain amplifier?
    digital Pot (Ok).

    The above two should be instantaneously ready for a new command.
    The command might not be executed immediately if the system is designed to change only on a zero-crossing in order to minimise glitches.

    DDS = direct-digital-synthesis? If so, this might take significant time to obey a command before it is ready for the next one. You'll have to work through the data sheet to see if this is so.

    As to matching, I did not mean that all the wires should be the same length.
    What I meant was that the electrical impedance of the wire should be matched / terminated at both the sending and receiving ends.
    When you send an pulse down a wire, it propagates at almost the speed of light. When it hits the far end, if the signal is not terminated, a pulse will be reflected back up the wire until it hits the transmitter. At this point, if the transmitter is also not matched/terminated, it will be reflected back down the wire again...
    Most of the time we do not need to worry about such effects. But they are real, and can pose problems if the wires are so long that the time-to-travel is a significant fraction of the smallest-pulse-time to which the devices can respond.

    Regards,
    Danish
    #4
    Tom Myers
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    RE: SPI reliability 2009/06/23 08:28:44 (permalink)
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    Hi Danish,
     
    You passed the acronyms test! wink (sorry I should have explained)!
     
    I would say that the impedances are matched.
     
    I am aware of the theory of transmission lines, reflection etc .... (I won't say I fully understand it!). Is there a sure way of "terminating" the SCK and SDI lines on breadboard (long tracks), or the fact that the SCK and SDI track sat somepoint is connect to the CLK and SDI pins, respectively?
     
    I have tried pull-ups and they don't help me, I will now try the series impedance matching idea!
     
    Regards,
    Tom
    #5
    asmallri
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    RE: SPI reliability 2009/06/23 08:37:03 (permalink)
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    ORIGINAL: danish.ali

    When you send an pulse down a wire, it propagates at almost the speed of light. When it hits the far end, if the signal is not terminated, a pulse will be reflected back up the wire until it hits the transmitter. At this point, if the transmitter is also not matched/terminated, it will be reflected back down the wire again...



    Hardly likely to be a problem in this case. Tom is talking about a low SPI clock rate of of less than 100K. At a worst case scenario of 100K the wavelength is 3000 meters. Assuming Tom is dealing with a cable length is less than 1 meter, this will not be a problem.

    Regards, Andrew

    http://www.brushelectronics.com/index.php?page=software
    Home of Ethernet, SD Card, and Encrypted Serial and USB Bootloaders for PICs!!
    #6
    danish.ali
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    RE: SPI reliability 2009/06/23 08:47:05 (permalink)
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    Hi Andrew,

    I disagree.

    Although the intended clock might be (say) 100 kHz, the reflections will give ringing which might be around 100 MHz.
    How will the SPI device respond to that? I'm not sure - they are designed to work at 10 MHz. Might you get double-clocking?

    Best regards,
    Danish
    #7
    Tom Myers
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    RE: SPI reliability 2009/06/23 09:02:48 (permalink)
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    Hi,
     
    I have placed a 10K series resistor in each line (CLK and SDI) and now my signals have become saw tooth like! If I say monitor the CLK signal before the resistor and compare the SDI line after the resistor the data bit now ramps up and decays over 3 - 4 clock pulses!!?
     
    Any more ideas?
     
    Regards,
    Tom
    #8
    danish.ali
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    RE: SPI reliability 2009/06/23 09:20:22 (permalink)
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    You have a lot of stray capacitance - how long are the wires? Are they screened?

    Try changing the resistors to 100 ohms - they should now be fast enough (and probably a better match, but with higher current flowing so harder on your layout).

    Regards,
    Danish
    #9
    Tom Myers
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    RE: SPI reliability 2009/06/23 09:25:06 (permalink)
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    Furthermore, do I need any series resistors?
     
    If may signals look good on the scope without any resistors, then should I be looking elsewhere for the intermittant communications? I always see the data and clock lines busy, sometimes the devices respond and sometimes they just ignore the commands! I am sure I have the timing sequence correct and in specification of the CLK, SDI and /CS lines as they do work at times.
     
    Regards,
    Tom
    #10
    asmallri
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    RE: SPI reliability 2009/06/23 09:49:33 (permalink)
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    ORIGINAL: Tom Myers

    Furthermore, do I need any series resistors?

    If may signals look good on the scope without any resistors, then should I be looking elsewhere for the intermittant communications? I always see the data and clock lines busy, sometimes the devices respond and sometimes they just ignore the commands! I am sure I have the timing sequence correct and in specification of the CLK, SDI and /CS lines as they do work at times.

    Regards,
    Tom


    Adding those series resistors created another problem. I am sure your problem is elsewhere.

    Regards, Andrew

    http://www.brushelectronics.com/index.php?page=software
    Home of Ethernet, SD Card, and Encrypted Serial and USB Bootloaders for PICs!!
    #11
    lbodnar
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    RE: SPI reliability 2009/06/23 12:42:23 (permalink)
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    At 10kHz SPI rate even valves should work fine...
    I wonder if your problem lies in the wrong SPI mode selection? Sampling data at the trailing edge of the clock instead of the front edge might marginally work but be wrong.
    You don't use capacitors on SPI signal lines by any chance do you? I am sure not. Unless you use gentle RC filtering with 47R and 30pF or so...
    Are your slaves powered properly and by the spec? You are not phantom powering them through data lines?
    I've run out of ideas so far.
    post edited by lbodnar - 2009/06/23 14:39:32

    Leo
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    eriklidgren
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    RE: SPI reliability 2009/06/23 13:14:18 (permalink)
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    Have looked at cs release against the last bit to make sure it is completely done before you release cs?
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    Tom Myers
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    RE: SPI reliability 2009/06/23 13:25:37 (permalink)
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    Hi,

     
    I wonder if your problem lies in the wrong SPI mode selection? Sampling data at the trailing edge of the clock instead of the front edge might marginally work.


    I have taken note of this and paired devices on two SPI ports according to their mode selection, however, I will double check the datasheets to make sure that I am correct. For example, I have interpretted that the MCP41010 (Microchip) Digital POT which I am using clocks data on the rising idle to active? Therefore, I have clear the CKE bit of SPI1CON - can anyone verify this from the datasheet?

     
    You don't use capacitors on SPI signal lines by any chance do you? I am sure not. Unless you use gentle RC filtering with 47R and 30pF or so...


    No, the lines are directly connected from MCU to the slave devices.

     
    Are your slaves powered properly and by the spec? You are not phantom powering them through data lines?
    I've run out of ideas so far.


    Yes. I have doubled ckecked this. I am also powering everything from the Explorer 16 which has a LM117 regulator which is capable of delivering 1.5A, the power supply used to power this had a current of 700mA, and I am no way near this limit.

     
    Have looked at cs release against the last bit to make sure it is completely done before you release cs?


    Yes. Plus a bit extra! I have made sure the CS is released before the following clock edge, but the following data stream on SPI does not occur for 1ms after the previous data event.

    Regards,
    Tom
    post edited by Tom Myers - 2009/06/23 13:27:42
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    lbodnar
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    RE: SPI reliability 2009/06/23 14:35:41 (permalink)
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    ORIGINAL: Tom Myers
    I have interpretted that the MCP41010 (Microchip) Digital POT which I am using clocks data on the rising idle to active? Therefore, I have clear the CKE bit of SPI1CON - can anyone verify this from the datasheet?
    This seems to be the other way. Looks like CKP=0, CKE=1 to me.
    post edited by lbodnar - 2009/06/23 14:45:13

    Leo
    #15
    Tom Myers
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    RE: SPI reliability 2009/06/23 16:06:22 (permalink)
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    quote:

    ORIGINAL: Tom Myers
    I have interpretted that the MCP41010 (Microchip) Digital POT which I am using clocks data on the rising idle to active? Therefore, I have clear the CKE bit of SPI1CON - can anyone verify this from the datasheet?

    This seems to be the other way. Looks like CKP=0, CKE=1 to me.

     
    Ha interesting! I had CKP = 0 and CKE = 0 this is for SPI2 where I have MCP41010.
     
    On SPI1 I have an MCP6S91 (PGA), 2 x LTC1391 (Analogue switches) and a AD5932 (DDS) operating  with CKE = 0 and CKE = 0. I am also experiencing the same reliability problems on all these devices. That is why I was suspecting hardware, rather than software settings!?
     
    Regards,
    Tom
    #16
    lbodnar
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    RE: SPI reliability 2009/06/23 16:45:34 (permalink)
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    ORIGINAL: Tom Myers
    That is why I was suspecting hardware, rather than software settings!?
    Famous last words grin

    Leo
    #17
    lbodnar
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    RE: SPI reliability 2009/06/25 01:44:21 (permalink)
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    Hi Tom,
    Have you made any progress?
    Cheers

    Leo
    #18
    Tom Myers
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    RE: SPI reliability 2009/06/25 14:44:11 (permalink)
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    Hi Leo,
     
    I took your advice!
     
     
    This seems to be the other way. Looks like CKP=0, CKE=1 to me.

     
    And so far so good!!!!
     
    Regards,
    Tom
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