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P24FJ framed SPI slave mode

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guynoir
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2009/05/27 07:39:29 (permalink)
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P24FJ framed SPI slave mode

Hello all,

I am trying to use 24FJ256GA106 as an "SPI and frame slave" to communicate with a device that provides a 3 MHz clock. The data packets are 32-bits and they are sent with 1 kHz rate. The device also provides a Fsync signal beginning with the first data bit and going low after the last bit of each packet, i.e., Fsync is high while there is data on the data line.

Previously I used dsPIC30F4013 which has no enhanced buffer, and I was able to read from the device in 16-bit mode, while missing the first bit of each word. I thought (and still think that that was because dsPIC30F4013 has no frame synch pulse edge select option (SPIFE) ).

With the 24FJ I am unable to read from the SPI interface neither with enhanced buffer mode nor without it.

I did the peripheral PIN assignements, lock, unlock and TRIS settings.
I am using CCS C compiler
My clock is at 24 MHz with PLL (6MHzx4)
I checked and disabled ADC pins, they are all digital I/0.
I am not using the interrupts, I am checking the SPIRBF in regular mode to grab each word, or the SPIBECx  in enhanced mode to see two unread words. 

In regular mode, once SPIRBF is set, I can only get all O's.

In enhanced mode, the   SPIBECx  bits never seem to be set.

Any thoughts?



Here is my SPI initialization:

void initSPI_1(){
    SPIEN1 = 0;
    SPI1BUF = 0x0000;
    // We are not using SPI interrupts in PIC24FJ, using Fsync instead
    SPI1IF = 0;
    SPI1IE = 0;
    SPISIDL1 = 0; //continue module operation in the idle mode
    DISSDO1 = 1; // SDOx pin is not used by module; pin functions as I/O
    MODE161 = 1; // Communication is word-wide (16 bits)
    SMP1 = 0;    // SMP must be cleared when SPIx is used in Slave mode.
    CKE1 = 0;    // The CKE bit is not used in the Framed SPI modes. The user should program this bit to '0' for the Framed SPI modes
    SSEN1 = 0;   // the state of slave select ignored
    CKP1 = 1;    // Idle state for clock is a high level; active state is a low level
    MSTEN1 =  0; // slave mode
   
    FRMEN1 = 1;   // Framed SPIx support enabled
    SPIFSD1 = 1;  // Frame sync pulse input (slave)
    SPIFPOL1 = 1; // Frame sync pulse is active-high
    SPIFE1 = 1;   // Frame sync pulse coincides with first bit clock
    SPIBEN1 = 1;  // Enhanced Buffer enabled
   
    // Clear the SPIROV bit (SPIxSTAT<6>).
    SPIROV1 = 0;
    // Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>), this has to be done the latest, otherwise registry modifications are not possible
    SPIEN1 = 1;

}
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1 Reply Related Threads

    Neiwiertz
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    RE: P24FJ framed SPI slave mode 2009/05/27 13:28:50 (permalink)
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    Give it a browse here which could be helpfull E16 Communicate between 2 boards by SPI
    (i added your one about framed spi)

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