The PIC24 SPI slave problem SOLVED
There are a lot of topics concerning problems using the SPI module of PIC24 in slave mode. The typical scenario is a bus with many devices such as DACs, EEPROMS etc. and among them a PIC24 slave with #SS pin enabled. The problems in short are: the PIC slave receives all the traffic on the bus no matter the state of the #SS pin, the SDO pin of the PIC slave sometimes does not goes tri-state thus causing bus conflicts, eventually the slave and master go out of sync an communication totally fails.
There is a workaround proposed by microchip's errata sheets http://ww1.microchip.com/downloads/en/DeviceDoc/80316g.pdf
errata 18, but following it is sometimes quite unacceptable, because of the time spent checking for the right data to come.
So what I've tried to do is to externally mimic the functionality of the module to make it act as described in the datasheet. Here is the simple schematic using only 2 external components namely 74AHC1G125 and 74AUP1T97:
The 74AHC1G125 is used to enable the SDO pin only when the #CS is active and there is no other device to use the line, while the 74AUP1T97 guarantees that clock signals will get to the slave again only when #CS pin is active thus the slave receiving only data that is directed to it.
In my application I have left the #SS pin of the slave connected as well as enabled in the module but maybe it is just obsolete using the above schematic.
The SPI module of the slave now just works perfectly like any other slave device on the line.
The problem of losing sync with the master is also solved, but if a restarted data exchange is desired the only way to do this I've found to be an SPI module disable/enable sequence.
That's my solution to the problem. I hope that someone will find this post useful :)
post edited by shondll - 2009/05/12 15:05:55