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The PIC24 SPI slave problem SOLVED

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shondll
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2009/05/12 15:02:29 (permalink)
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The PIC24 SPI slave problem SOLVED

      There are a lot of topics concerning problems using the SPI module of PIC24 in slave mode. The typical scenario is a bus with many devices such as DACs, EEPROMS etc. and among them a PIC24 slave with #SS pin enabled. The problems in short are: the PIC slave receives all the traffic on the bus no matter the state of the #SS pin, the SDO pin of the PIC slave sometimes does not goes tri-state thus causing bus conflicts, eventually the slave and master go out of sync an communication totally fails.
   There is a workaround proposed by microchip's errata sheets http://ww1.microchip.com/downloads/en/DeviceDoc/80316g.pdf errata 18, but following it is sometimes quite unacceptable, because of the time spent checking for the right data to come.
   So what I've tried to do is to externally mimic the functionality of the module to make it act as described in the datasheet. Here is the simple schematic using only 2 external components namely 74AHC1G125 and 74AUP1T97:


    The 74AHC1G125 is used to enable the SDO pin only when the #CS is active and there is no other device to use the line, while the 74AUP1T97 guarantees that clock signals will get to the slave again only when #CS pin is active thus the slave receiving only data that is directed to it.
    In my application I have left the #SS pin of the slave connected as well as enabled in the module but maybe it is just obsolete using the above schematic.
   The SPI module of the slave now just works perfectly like any other slave device on the line.
    The problem of losing sync with the master is also solved, but if a restarted data exchange is desired the only way to do this I've found to be an SPI module disable/enable sequence.

That's my solution to the problem. I hope that someone will find this post useful :)

post edited by shondll - 2009/05/12 15:05:55

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    sequoia
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    RE: The PIC24 SPI slave problem SOLVED 2009/05/13 06:39:21 (permalink)
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    Looks like a VERY interesting approach. You may be able to simplify it some if you want, though. Try connecting the slave CS directly to ground as you suggested. Assuming that works – and it should – then invert the master CS output in PIC SW. Then you can then use one AND gate CS and CKL to drive the slave CKL. A second AND gate CS and slave SDO to the PIC SDI completes your functionality. A total of two AND gates replacing the eight assorted gates you specified.
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    shondll
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    RE: The PIC24 SPI slave problem SOLVED 2009/05/16 09:03:00 (permalink)
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    Well, I don't think that the second AND gate will do the job, because it's a 3-state element that is needed. The problem I encountered was that SDO of the slave sporadically goes output and blocks traffic on the bus, whether it's 1 or 0 doesn't matter because of the conflicting outputs. The 3-state element disables the SDO of the slave when not in use, turning it to low state is just not enough.
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    sequoia
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    RE: The PIC24 SPI slave problem SOLVED 2009/05/17 05:15:11 (permalink)
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    Good point! So the one AND gets replaced with a tri-state buffer. And because they generally require an active-low chip select, an inverter is needed. Three gates total.

    Also, as the inverter makes both CS and NOT-CS available, no need to change SW and the slave CS can remain connected if desired.
    post edited by sequoia - 2009/05/17 05:26:18
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