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SPI with DMA : Tx only in Master mode

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cbarn
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2009/03/22 19:47:25 (permalink)
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SPI with DMA : Tx only in Master mode

Hi,

I'm wondering how to configure the SPI and DMA of the 33FJ128MC706 to operate in "Tx only master mode".

The goal is to use a single DMA channel to transmit the data.  Without this Tx only mode, it appears that 2 DMA channels must be allocated to send data.  One channel to send the data, and the othre to read the SPI RX BUFFER to keep it from overflowing.

Thank you in advance,
Chris
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4 Replies Related Threads

    cbarn
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    RE: SPI with DMA : Tx only in Master mode 2009/05/19 12:32:41 (permalink)
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    Microchip - is there a way to do this?
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    tilly
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    RE: SPI with DMA : Tx only in Master mode 2009/05/21 08:14:11 (permalink)
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    Hi cbarn,
    I did quite a lot with SPI, and I never got that running - would be nice to use only on DMA channel for TX!
     
    Unfortunately the Overrun Bit blocks any further SPI activity.
     
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    ChrisJ
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    Re: RE: SPI with DMA : Tx only in Master mode 2010/07/29 01:56:40 (permalink)
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    Hi there,

    i know this threat is a bit older, but I`m trying to find a solution to the exact same problem: Using just one DMA-Channel for SPI-Tx.

    Did you get this to work?
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    tilly
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    Re: RE: SPI with DMA : Tx only in Master mode 2010/07/29 02:17:44 (permalink)
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    Hi Chris,
    I just got your request on my Email account - but I think you better should ask this question to cbarn.

    Concerning me, I still think that it is possible only with 2 DMA channels - the reason is that you have no possibility to skip the received bytes. Meanwhile the MC710 processors are produced in a new silicon redesign, they call it MC710A, having a much smaller errata sheet. But this "problem" with the SPI DMA was not really an errata, it is just requirement of the processor (as it is not possible to skip the received bytes, and as stupidly the SPI interface will stop working on receive overflow ). So I am frightened it still did not change, you will need 2 DMA channels for SPI handling.
    #5
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