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Can excessive use of DMA clog up the data bus?

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modulem
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2008/12/13 22:34:35 (permalink)
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Can excessive use of DMA clog up the data bus?

Hi all,

I'm thinking of using the DMA and PMP modules together to update an external LCD. Let's say that I'm transferring data with the DMA at high frequencies (say, every 80 bytes every 79 us): Would this interfere with, for example, the prefetch cache, such that the performance of the CPU is affected?
post edited by modulem - 2008/12/13 22:38:58
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    Deenayd
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    RE: Can excessive use of DMA clog up the data bus? 2008/12/14 07:26:31 (permalink)
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    DMA will alway use shared buses, so it can slow down CPU.
     
    Basic ways to minimize this effect:
     
    1) Use arbitration mode 0
     
    2) Always align copied data
    Unaligned copies causes multiply bus accesses per copied word / dword and (unless I'm mistaken) arbitration can't suspend DMA access inside one DMA transaction
     
    3) Copy from/to RAM, not from FLASH (unless you work with up to 30MHz CPU clock)
    Copying from FLASH uses FLASH for multiply CPU cycles (wait states) and this slows down procesing
     
    4) Suspend DMA if you can't afford loosing even single CPU cycle in time critical code

    Slawek Piotrowski
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    modulem
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    RE: Can excessive use of DMA clog up the data bus? 2009/06/19 19:19:47 (permalink)
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    I need to exchange 32 bytes between two PIC32 units, as often as I can. My plan is to hook up input and output DMA modules with the SPI port in each of the two ucs. However, there is also a timer (T3) that interrupts every 500us, and reads from the A/D and executes code, all within 20us. This occurs on both ucs, although not necessarily at the same time. Will DMA activity slow down reads from ADC1BUF*?

    In any case, let's say I want to freeze all SPI/DMA activity for the duration of my T3 interrupt. I could write a '1' to DMACON.SUSPEND at the beginning of my ISR, and a '0' at the end. Since DMA activity would halt (albeit temporarily), how would this affect the integrity of the SPI transmission? Could the bytes of the communication payload become somehow "shifted"?

    Thanks.
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    Deenayd
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    RE: Can excessive use of DMA clog up the data bus? 2009/06/21 22:28:25 (permalink)
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    I'd suggest doing a little testing. After each received word from SPI DMA will use data bus for two cycles (read and write) - this shouldn't matter much when your time frame is 20us (1600 cycles).

    Yes, you can suspend DMA, this will not shift bits in SPI. This can slow down SPI on SPI master (a delay beetween bytes). It could miss byte(s) if SPI buffer was not big enough to buffer SPI data (on SPI slave). Calculate if it may happen to you; use 32 bits SPI if you're close. Remember suspending SPI also takes cycles.

    Slawek Piotrowski
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