RE: SPI 18F4455 problem with SS pin in master mode (incredible)
2008/09/24 08:49:57
(permalink)
More info about this SPI problem... i set RA5 as output and changes on RA5 state after and before SPI transacction don't create any trouble, but any change of RA5 during SPI transacction (in my case, while i'm pulling SSPIF) SDO data is incorrect, seems like RA5 "cuts" SDO. So, this problems is not related with RA5 direction. I can change my design to avoid state changes of RA5 during SPI activity, but... is the SPI block of the 18F4455 reliable? (Tengo miedo nene!!!)