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SPI 18F4455 problem with SS pin in master mode (incredible)

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mfviero
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2008/09/23 18:09:23 (permalink)
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SPI 18F4455 problem with SS pin in master mode (incredible)

I'm translating a 16F877 code to a 18F4455 that use SPI to read data from a 25CXXX memory, this program works perfect in the 16F877(A), but when i run this code (translated to 18F) don't work and do this: runs perfect until any change of state occurs on RA5/AN4/HLVDIN/-SS/C2OUT, ADCON1=0Fh (all i/o digital), comparator OFF, SSPCON1= 00100010b (ENABLE, mode MASTER FOSC/64, also try FOSC/16 and /4) HLV set as default: OFF, it seems like the SS pin (RA5 is set as input) modified SDO -remember i set SPI as MASTER!!!!-... so... any idea?
Funny thing: this only happens on change of state of SS pin, if SS pin is set (SS disable in slave) SPI works fine...
I'm clueless and 2 days expended in this... any idea to solve this will help. thanks!
post edited by mfviero - 2008/09/23 18:11:45
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    dhenry
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    RE: SPI 18F4455 problem with SS pin in master mode (incredible) 2008/09/23 21:34:33 (permalink)
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    There are six separate errata documents for the '4455; too many for me to look through for you.  Have you checked them?
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    mfviero
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    RE: SPI 18F4455 problem with SS pin in master mode (incredible) 2008/09/24 06:00:41 (permalink)
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    Yeap, after one day with this problem i download all erratas PDF for the 18F4455 family and nothing fits with this problem, i also check for unexpected interrupts o resets asociated with the SS pin with no results, the CPU runs perfect. But i agree with you... too many erratas for one device. Thanks for the post dhenry
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    mfviero
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    RE: SPI 18F4455 problem with SS pin in master mode (incredible) 2008/09/24 08:49:57 (permalink)
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    More info about this SPI problem... i set RA5 as output and changes on RA5 state after and before SPI transacction don't create any trouble, but any change of RA5 during SPI transacction (in my case, while i'm pulling SSPIF) SDO data is incorrect, seems like RA5 "cuts" SDO. So, this problems is not related with RA5 direction. I can change my design to avoid state changes of RA5 during SPI activity, but... is the SPI block of the 18F4455 reliable? (Tengo miedo nene!!!)
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    Dany
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    RE: SPI 18F4455 problem with SS pin in master mode (incredible) 2009/08/18 01:37:24 (permalink)
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    Hi, I have seen exactly the same problem, but now in a P18F2620, see http://www.mikroe.com/forum/viewtopic.php?t=19724&start=3. I wanted to use the portA pins of it all as analog inputs, and to keep SPI working correctly I had to make RA5 output and leave it alone. sad
    Seems to be a generic MSSP problem?
    post edited by Dany - 2009/08/18 01:44:39

    Kind regards,
    Dany
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