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SimyXT
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2012/02/13 07:40:33 (permalink)
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ADC Protection (final solution)

Hello! After a long search in this forum with no solution in the discussions because it is often vague, I would like to explain my problem. I'm designing a board that includes 6-channel ADC and then will be sold. Should I make sure that the end user does not destroying the PIC or channel ADC from overvoltage and so I would look for a solution that would limit the voltage on ADC channels. The first idea was obviously the zener in parallel to the channel, which limits the voltage to 5.1V. But in reading various posts, the zener is not an effective solution because it would cause an error reading in the channel and I would like to maintain the accuracy provided by the PIC. Other solutions involve the use of a Schottky diode, but as is used? Thank you, Simone
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SimyXT
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Re:ADC Protection (final solution) 2012/02/16 14:37:31 (permalink)
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No solutions?
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Steven37
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Re:ADC Protection (final solution) 2012/02/16 16:23:24 (permalink)
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Hi,

This is how I protected the A/D inputs that went off my PCB. The dual schottky diode clamps the input to the supply rails, the 470R protects the low current protection diodes in the PIC, the 1k resistor limits the input current when voltage is above or below the supply.

The total source resistance is 1470 ohms which is below the maximum of 2.5K recommended by Microchip.

The BAS40-04 has a current rating of 120mA and a leakage of about 1uA.

Regards Steve.

EDIT:-  If you are using a low current power supply for the PIC it is possible that an over voltage on one of the protected A/D inputs could cause the power supply voltage to be raised to a point that you could damage the PIC. If so you could add a zener diode across the power supply to clamp the supply voltage to a safe level. ie. on a low current 3.3V supply you could use a 3.6V 1W zener like a 1N4729A, for a 5V supply you could us a 5.6V 1W 1N4734A.

Corrected schematic



post edited by Steven37 - 2012/02/16 17:29:04

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Ian.M
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Re:ADC Protection (final solution) 2012/02/16 17:48:31 (permalink)
+2 (1)
Top clamp to Vss? I think NOT.  Thanks for fixing that ! LoL

The other problem is that is is dangerous to let the clamps dump into the supply rail.  It can be OK if you can always guarantee that  there will always be enough load on the supply to handle the maximum possible clamping current, but unless you are using a shunt regulator, the clamping current can easily pull the supply above its proper voltage and even destroy all chips connected to it.

Schottky diodes dumping into a shunt regulated Vdd rail can do what you need.  Unfortunately you then get all the power dissipation problems of shunt regulators.  You cant just use a separate shunt regulator for the clamping rail, as if the tolerences stack up in an undesirable direction, you could easily end up with Vdd 10% less than the clamping rail, in which case it might as well not even be there. sad

You can maintain the base of a PNP transistor one diode drop below the Vdd rail, with the collector to ground and clamp to the emitter, but unless you use a dual transistor with one device diode connected, the diode drop is unlikely to track Vbe closely enough.



R4 and C1 maintain bias on the upper clamping diodes and provide decoupling so you don't get crosstalk. Repeat D1,D2,R1,R2 for as many signals as you need to clamp.   N.B. the 1K base resistor provides over 200mA of clamping capability assuming a minimum HFE of 50.  Decrease it if you need more clamping,subject to the transistor's IC_Max.
 
Edit: N.B Q1A, Q1B should be a dual transistor in the same package if you can get one suitable, or at least should be closely matched and thermally coupled.  (i.e. SMD from same reel with base leads in close proximity on the same pad, and possibly a small strip of copper tape over the top of the packages)
post edited by Ian.M - 2012/12/04 07:54:45

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Ian.M
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Re:ADC Protection (final solution) 2012/02/16 18:09:22 (permalink)
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@Stephen37,
Unfortunately component tolerances for affordable Zeners aren't that tight so there is no way of guaranteeing that any Zener that clamps the Vdd rail is going to do so below the maximum permitted supply voltage and NOT conduct significantly at the nominal supply voltage.   Add to that the problem that if the regulator output is at the high end of its tolerence range, and the Zener at the low end, you have the potential to have a rather hot and unhappy Zener and regulator. To do it RIGHT using your circuit, use a TL431B precision shunt adjustable reference + two precision resistors to set it to 5.40V +/-1% for a nominal 5V supply +/- 5% and a PIC abs Max Vdd of 5.5v.

 With the requirement for a precision reference and precision resistors, it is hard to justify the expense - unless you set it for 4.1 V and feed the ADC Vref from it as well ( for a nominal 4mV/count to make the maths easier in the software) with a resistor to Vdd to bias it.
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Steven37
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Re:ADC Protection (final solution) 2012/02/16 20:57:08 (permalink)
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Ian.M
Unfortunately component tolerances for affordable Zeners aren't that tight so there is no way of guaranteeing that any Zener that clamps the Vdd rail is going to do so below the maximum permitted supply voltage and NOT conduct significantly at the nominal supply voltage.


Hi Ian,

You are correct, just checked the specs on the zeners.
I didn't need to use a zener, I didn't worry about the supply rail being forced high due to an input over voltage, because my PCB was powering a lot of other circuitry, the power supply was delivering over 1A. So the over-voltage would need to force a total of more than 1A through the protection diodes.

Even if all 4 of my A/D inputs were forced to 200V there would not be enough current to over-ride the 1A load on the supply.
I did not design my circuit to be bullet proof, an over-voltage of 200V for over 10mS would destroy the schottky diodes (I=V/R = 200/1000 = 200mA. diodes rated at 120mA continuous, 200mA < 10mS)

Regards Steve,
post edited by Steven37 - 2012/02/16 21:06:55
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SimyXT
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Re:ADC Protection (final solution) 2012/02/17 08:34:56 (permalink)
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I finally found what I was looking..
Really thanks for solutions and a bit of school! :-)
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Ian.M
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Re:ADC Protection (final solution) 2012/02/17 08:37:22 (permalink)
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To wrap the topic up, please tell us what solution you are going for, and after testing, how well it works for you. wink
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MrStive
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Re:ADC Protection (final solution) 2012/06/14 04:49:59 (permalink)
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Hi Ian,
Can you please explain how the current mirror works in your setup? I hate those things.
I'm hoping to use a similar setup to protect my ADC and want a firm understanding of how it triggers.
Does it turn on when clamping rail>Vdd?
 
Thanks for your help in advance.
Stive
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bonedoc
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Re:ADC Protection (final solution) 2012/06/15 09:13:14 (permalink)
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Hey guys, I am sorry I never gave a summery. I didnt realize anyone ever responded! MrStive, if you can give me a specific question, I can try to answer.
 
Thanks to Ian M's great advice, everything is working without a hitch. As far as hardware goes, There is:
 
-A charging section. This is a high current booster that takes a 12V battery and charges it to 300V in 2 seconds. The single most important thing to remember is inductor saturation. if you saturate it and the induction drops, you are going to be drawing so much current that you will melt the PCB or the switching MOSFET. Your best bet is to calculate the max on time based on the inductor max current, inductance, and input voltage. Once this is established, it is important to select a switch with a low gate resistance and charge....and remember to see how fast it can turn on and off. Otherwise, this will cause it to melt. Remember, if you have a 1:10 inductor and there is 300V on the secondary side, you may need a larger or better protected MOSFET.
 
-A high voltage monitoring branch. My circuit is dependent on voltage. So, I am measuring this, and not current. I have a voltage divider and the upper (power) branch consists of 2- 1MOhm 1/2W resistors to divide the high voltage and power up. The lower arm is a 5K pot so the device can be calibrated with variations. For extra protection, I have a BAT43 on the pot, and a 1k resistor between the pic and the pot. I also have a 22uF tantalum cap on the ADC pin. The thing to remember is you can charge the caps on the secondary faster than you can sample, especially in lower voltages. They say a capacitor takes "forever" to completely charge or discharge. So, I have a little formula that translates the ADC sample to a CPP duty value. The lower voltages have a lower duty. As the value of the cap voltage goes up, the duty gets large. You can go balls to the walls fast...but things will overheat or short. Be sure to test this with your most aggressive battery you plan to use. Just when you think you are good and you try a battery with a slightly high voltage, the di/dt curve will drastically change, and things will melt.
 
-A discharge circuit. I wanted my circuit to discharge automatically on power off. I also wanted to discharge if a voltage overshoot happens. So, if I am ever 10V over my goal, I discharge to 10 below the limit and then charge back up to the goal at the duty cycle assigned to that range. You want to be careful that you dont get a ping pong thing going where it bounces between charge and discharge. I also recommend debouncing the code on a charge or discharge. When a discharge is used,  I would also have a short delay so that the the boost charger is not charging while the relay is closing...otherwise you may get a spark.You also need a large power resistor between the HV and the relay. I have a 5k 25W and have never had an issue with heat. It will discharge 300V to safe in just a few seconds.
 
I hope this helps! It was a fun project for me. I learn a lot here. I have a friend who is using the circuit right now....seeing if he can melt or break anything.
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Ian.M
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Re:ADC Protection (final solution) 2012/06/15 11:11:47 (permalink)
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As the load is in the emitter circuit, not the collector circuit, it is *NOT* a current mirror.  It is actually a PNP emitter follower with its base held one Vbe drop below the Vdd rail.    It therefore provides a stiff clamping sink maintained at the same voltage as the Vdd rail.
 
Bonedoc's circuit resembles a high energy camera flash.  His ADC protection requirements are quite severe . . . .
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MrStive
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Re:ADC Protection (final solution) 2012/06/15 16:32:02 (permalink)
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Hey guys,
Thanks for the information! Much more than I was expecting/hoping for.
My project is a 3-phase DTC Induction motor drive, where I need accurate voltage readings of the 3-phases. The phase voltages will be a square wave pulse which can last just 5uS. As the switching will involve 100's of amps, I'm expecting BIG voltage spikes!
 
I'm planning to scale the voltage 131:1 (400V->3.05V) for my 3v6 ADC port. I will take the voltage reading just before I need to issue a new switching state so hopefully the signal will have settled to either its high or low state. I'm thinking of allowing about 2.5uS for the signal to settle, and the other 2.5uS to take the samples.
As it should be a DC signal (at either high or low), I would like to add in a filter capacitor to block any noise, but I'm having trouble sizing it so its 5*RC < say 2.25uS (the slew rate of my opamp to get from 0-3.6V). Bonedoc, this sounds similar to your voltage monitoring branch, perhaps you can give me some insight?
 
What do you think the circuit?
Is the PNP emitter follower a good candidate here?

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bonedoc
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Re:ADC Protection (final solution) 2012/06/15 23:09:19 (permalink)
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Im happy with my voltage reading. All I can recommend:
 
-You may need efficient code or a fast processor if you are going to sample that much.
 
-Since my voltage regulators and resistors all have errors, my lower arm resistor is a pot so I can fine tune things. It really works good. I notice some error issues if you utilize all 10 bits of the ADC and left justify. I recommend simply right justifying the result and only using ADRESL so you dont hit the max ADC voltage. So, your HV would cause ADRESL to be = 255 when the ADC pin is 255/1023 = .249 of Vdd. You can then calculate your upper arm and lower arm resistor values to output this voltage when your load you are measuring is at its max.  I hope this makes sense.
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MrStive
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Re:ADC Protection (final solution) 2012/06/16 19:53:50 (permalink)
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bonedoc
-You may need efficient code or a fast processor if you are going to sample that much.

 
Yes, i plan to use a 210DMIPS cpu with 3 ADCs
 

bonedoc -Since my voltage regulators and resistors all have errors, my lower arm resistor is a pot so I can fine tune things. It really works good.

I'm hoping precision 0.1% resistors will be fine. In my experience i don't like to use pots as i find they can also de-tune themselves.
 
bonedoc
I notice some error issues if you utilize all 10 bits of the ADC and left justify. I recommend simply right justifying the result and only using ADRESL so you dont hit the max ADC voltage. So, your HV would cause ADRESL to be = 255 when the ADC pin is 255/1023 = .249 of Vdd. You can then calculate your upper arm and lower arm resistor values to output this voltage when your load you are measuring is at its max.  I hope this makes sense.

I'm hoping the clamp will keep the ADC one Vbe drop away from 3.6V ? I will need to change the opamp design though because it will hit the 0V rail and go into overload
post edited by MrStive - 2012/06/16 20:35:34
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MrStive
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Re:ADC Protection (final solution) 2012/06/17 01:48:36 (permalink)
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Updated circuit, what do you think?
 

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Ian.M
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Re:ADC Protection (final solution) 2012/06/17 01:59:32 (permalink)
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I'm not seeing a link to, or attachment of, your schematic.
If you want us to comment, please show us the circuit (in GIF, PNG or as a last resort PDF format, as most of us wont be able/willing to open proprietary schematic capture file formats)! wink
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MrStive
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Re:ADC Protection (final solution) 2012/06/17 02:06:40 (permalink)
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Oh, i don't know why,  it comes up on my screen....
 
Try this link: http://www.electro-tech-o...-adc-stiive-adc-v3.jpg
 
I now use an instrumentation amp
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Ian.M
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Re:ADC Protection (final solution) 2012/06/17 03:01:38 (permalink)
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Many websites prevent hot-linking to images by substituting something else or returning a HTTP error code. Basically images on such a site can only be displayed in their own pages.   If the site doesn't offer a  URL for use in forums, always check  image URLs can be opened in another browser that has *NOT* been used to visit the page you found them on before using them here.
 
N.B. using third party hosted content without permission is extremely rude  as the target site gets the bandwidth costs without any benefit.  Providing an link to their page containing the content at least provides some compensatory traffic and reduces the chance that the sysop will choose to reconfigure their site to block it or serve you something undesirable (e.g. a rude message about bandwidth theft or occasionally even seriously NSFW fetish images that nearly everyone would rather they had NEVER seen) instead of the content you thought you were displaying.
 
Also, don't expect anyone here to register with another site just to view your images . . . . sad

post edited by Ian.M - 2012/06/17 03:19:36
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MrStive
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Re:ADC Protection (final solution) 2012/06/17 04:12:15 (permalink)
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Ohh, didn't realise.
This should work.

 
Thanks for your help
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Ian.M
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Re:ADC Protection (final solution) 2012/06/17 06:53:30 (permalink)
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The instrumentation amp's output cas the potential to swing more than +/- 4V.  This will exceed the maximum +ve ADC input voltage for all 3.3V PICs and the maximum negative ADC input voltage for ALL PICs.  The question is: Does your clamping circuit guarantee the output doesn't hit the rail?
 
You have not shown a gain programming resistor for the INA129.  I assume that this is deliberate and you are using it as a unit gain difference amplifier.   Even so, i would not trust the output to track the input if you have exceeded the input common mode range. Also it may hit the rail during power-up or power-down transients.
 
Finally you -ve BAT54 clamp appears to be connected to a resistive divider so will not only be ineffective but will also pollute the -312.5 mV rail during any negative transients.
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