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List of PIC32 Errata And Manual Errors

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2011/09/12 08:31:50 (permalink)
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List of PIC32 Errata And Manual Errors

I have found several problems with the PIC32 reference manuals, as well as a few pieces of errata relating to the chip itself.  They are listed below.  If anyone has any other errata related to the PIC32, or if they would like to confirm/dispute my findings, please feel free to add them to this thread.
NOTE:  "the data sheet REV F" refers to DS61156G, located at.
http://ww1.microchip.com/...n/DeviceDoc/61156G.pdf

1)  I2C1ADD at register address 0x5320 is erroneously called I2C3DD in the data sheet REV F, this was found out by comparing with P32mx795f512l.h

2)  I2C2ADD at register address 0x5420 is erroneously called I2C4DD in the data sheet REV F, this was found out by comparing with P32mx795f512l.h

3)  I2C3ADD at register address 0x5020 is erroneously called I2C5DD in the data sheet REV F, this was found out by comparing with P32mx795f512l.h

4)  C2RXM1 has a register address of C0A0 in the data sheet REV F, but its address is really C090, this was found out by comparing with P32mx795f512l.h

5)  C2RXM2 has a register address of C0B0 in the data sheet REV F, but its address is really C090, this was found out by comparing with P32mx795f512l.h

6)  LATD<x> is called "LAT<x>" in the PIC32MX795F512L datasheet REV F on page 94 in the register map for the "L" devices

7)  The word "speed" is probably missing after the word in the phrase "be selected for high conversion." in the note on page 20 of DS61104D.
(see ADC data-sheet)  http://ww1.microchip.com/...n/DeviceDoc/61104E.pdf

8)  Register TPTMR in DS-61108E is called IPTMR in the PIC32MX795F512L datasheet REV F, this causes confusion since the naming is inconsistent between the documents.
(see interrupt controller data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61108F.pdf

9)  Section 8.3 of DS-61108E indicates that the interupt vector number is 5 bits wide.  It is in fact 6 bits wide since there are 64 possible interrupt vectors and VEC<5:0> is used throughout the document.
(see interrupt controller data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61108F.pdf
NOTE:  This error appears to have been fixed in REV F of the document.

10)  Equation 29-1 in DS61125E should probably read 32768 not 32758.
(see RTCC data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61125E.pdf

11)  Section 19.3.4.2 of DS61110E says "Comparator output and interrupt generation is illustrated in Figure 19-4", but it is actually shown in Figure 19-3
(see comparator data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61110E.pdf

12)  The comparator input pin model shown in Figure 19-4 of DS61110E does not make sense.  VDD should not be connected directly to Ain.
(see comparator data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61110E.pdf

13)  Page 42 of DS61126F has a comment about USBFRZ that seems to be misplaced.  The comment should really appear on page 34.
(see USB data-sheet)  http://ww1.microchip.com/...n/DeviceDoc/61126F.pdf

14)  The A/D converter interrupt of the PIC32MX795F512L will not clear unless ADC1BUFx is read.  This does not appear to be documented in the ADC data-sheet.
(see ADC datasheet)  http://ww1.microchip.com/...n/DeviceDoc/61104E.pdf

15)  In DS-61154A page 24, "23" is super scripted in "RXOVF23", but it should not be superscripted.
(see CAN datasheet)  http://ww1.microchip.com/...eviceDoc/DS-61154A.pdf

16)  In DS-61154A page 44 the description of CiFIFOBA says "work-aligned in system RAM".  It should say "word-aligned in system RAM".
(see CAN datasheet)  http://ww1.microchip.com/...eviceDoc/DS-61154A.pdf

17)  CiCON<13> is called SIDLE in DS-61154A but it is called SIDL in the data structure defined in P32mx795f512l.h.  The datasheet differs from the microchip header file.
(see CAN datasheet)  http://ww1.microchip.com/...eviceDoc/DS-61154A.pdf

18)  The four step procedure for processing receive CAN messages shown in DS-61154A sec 34.6.3 is incomplete. CANiIF in IFS1 does not clear at the when UINC bit is set in CiFIFOCONn following a message receive.  In addition to clearing the interrupt souce within the CAN module, the bit in IFS1 must be cleared manually at the MCU level, which is not shown.
(see CAN datasheet)  http://ww1.microchip.com/...eviceDoc/DS-61154A.pdf

19)  DS61155A page 81.  The BYTE_COUNT field should indicate bytes received not bytes transmitted.  This appears to be a copy/paste error from page 79.
(see Ethernet datasheet table 35-8)  http://ww1.microchip.com/...eviceDoc/DS-61155A.pdf

20)  DS61117F page 13.  The description for bit 24 of DCRCCON indicates that CRCTYP is bit 15 of DCRCCON, but it is in fact bit 5 of  DCRCCON.
(see DMA datasheet)  http://ww1.microchip.com/...n/DeviceDoc/61117F.pdf

21)  TPTMR in DS-61108E is called IPTMR in the datasheet REV F.  The naming is inconsistent between the documents.
(see interrupt controller data-sheet) http://ww1.microchip.com/...n/DeviceDoc/61108F.pdf

post edited by forseeus - 2011/09/12 09:01:11
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