Each converter has 4 separate sample hold registers (at 10 bit mode), so it can sample simultaneously 4 (or 2 depending on the setup) channels, but it will perform the A/D conversations sequentially. In this case for one A/D trigger event there going to be 4 conversations and depending on the setup up to 4 A/D interrupts. This mode is for the case if it is important for you to take the 4 samples at the exact same moment. Unfortunately the limit is 4, unless you have a second A/D module, then you can sample 8 signals simultaneously.
I am making a rotary encoder, for this case it is important, that all the signals are sampled at the same moment otherwise at high speeds I can get erroneous results.
You can have 10 channels on one A/D by using channel scanning which is a sequential mode. For the 10 channels you will end up with 110 ksps sample rate.
Unfortunately the 1us is not possible for 2 channels. The throughput of the A/D module is 1100ksps. You have to divide it by the number of your channel. Even one channel can be tricky too, because you need a certain sampling time, in this case if you have 1 channel, then you will have less than 100ns for sampling. As I remember the module discharges the sampling capacitor after all conversation, and this also takes a few TAD time (which I am not sure about).
I would check if the output impedance of the analog source is small enough for the purpose. I can't tell the equation by heart, but it is in the reference manual. There is an RC circuitry, composed by the output impedance of the analog source, a 2K resistance of the switch inside the A/D module, some trace resistance of the chip (I can't remember it's value), and there is the holding capacitor. The question if the sampling capacitor can be charged within the available time within the 1 LSB error level.
In my case I use 940ksps simultaneous sampling on 2 channels. The TAD frequency is 13.1MHz, my source's output impedance is about 300 Ohms, and as I remember the calculated minimum sampling time was about 24ns. I receive valid data from the A/D module.
If you need higher sample rate there is the GS series of the 33EP family. I recently bought a PIC33EP128GS805 for my next project. It has 4 A/D modules each capable of 3.3 Msps. Unfortunately 3 of them has one dedicated channel, but one of the four is capable of channel scanning.
The sampling switch is 3K Ohms, the trace resistance is about 250 Ohms and the sample hold capacitor is 4.4pF. Minimum TAD is 76ns. Minimum sampling time is 2TAD. Conversion completion to sample start 0.5 TAD, with auto sampling. This all together is 14.5 TAD for one sampling/conversion period, means 14.5*76ns. That means 907ksps maximum without sequential sampling.
The simplest approach for me to calculate minimum sampling time is to use the RC time constant call it T. It is known that an RC circuit produces 33% error after T time of a 0-1 transition. After the second T time the error going to be 0.33*0.33 etc.
It is simple to get n where 0.33^n < 1/(2^10) for 10 bits. The number n going to be 7. So we need to wait 7 RC time for the signal to settle. In my case it was (3000+250+300)*4.4e-12 = 109ns. (not 24) The value of 2TAD (the minimum) is 152ns.
I checked my code I used sequential sampling, because some times the A/D couldn't finish before the new A/D trigger kicked in at 940ksps. (2 channel 470ksps per channel)
post edited by theozo - 2019/10/23 16:21:33