Hot!A minimalist RTOS for the PIC24

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Nicholas Lindan
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2017/03/09 11:38:57 (permalink)
4.5 (2)

A minimalist RTOS for the PIC24

CoRTOS - The world's simplest RTOS (?) is available under GPL V3
 (Update available, below)
 
It is fully documented, with a 30 page pdf manual and fully commented source code.
 
The intended audience includes:
  • Those needing a small footprint RTOS for moderately complex products such as IOT, appliances, industrial controls, sensors, and toys;
  • Students learning about Real Time techniques;
  • Makers wanting to program ‘close to the metal.’
 
CoRTOS has the following features:
  • Small kernel size of 16 lines of C, making it fast and reliable;
  • Simplified task design as there is no interference from preemption;
  • Full featured with add-on modules for delays and other time related functions, messaging, mutexes and signaling;
  • Designed and written in a straight-forward way, making it easy to understand and expand.
 
post edited by Nicholas Lindan - 2017/03/14 08:03:51

Nicholas Lindan
Cleveland Engineering Design, LLC
#1

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    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2017/03/14 07:29:22 (permalink)
    3.5 (2)
    Attached is a minor update to CoRTOS.

    CoRTOS now works with interrupts enabled at all times.

    CoRTOS is not a task scheduler.

    CoRTOS works like any other RTOS.  Tasks schedule themselves, picking up where they left off after making a call to the OS.

    Please feel free to send questions to nolindan@ix.netcom.com

    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #2
    bosco
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    Re: A minimalist RTOS for the PIC24 2017/03/15 06:50:08 (permalink)
    0
    GPLv3?  Why not a MIT or BSD type license?
     
    #3
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2017/05/13 14:33:25 (permalink)
    0
    A very minor update:
     
    Sending signals to the same counter by two interrupts of different priorities on RISC processors will need an interrupt enable/disable when incrementing the counter.  Many RISC processors can not atomically increment memory values.
     
    Hows that for obscure...

    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #4
    NorthGuy
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    Re: A minimalist RTOS for the PIC24 2017/05/13 16:25:59 (permalink)
    4 (2)
    Since when PIC24 is a RISC processor?
    #5
    picmadness
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    Re: A minimalist RTOS for the PIC24 2017/05/13 17:39:58 (permalink)
    3 (1)
    I don't think the PIC24 has a MMU or kernelspace/user space - how can you implement a RTOS? I guess as long as the software behaves it would work.
    #6
    qhb
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    Re: A minimalist RTOS for the PIC24 2017/05/13 18:22:03 (permalink)
    4 (1)
    It would need to be a cooperative RTOS, a preemptive one would be a nightmare.
     
    #7
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2017/05/13 18:40:12 (permalink)
    4 (1)
    NorthGuy
    Since when PIC24 is a RISC processor?

    You are right it isn't, but then it isn't really CISC, in the classical sense.  The RTOS isn't bound to a specific processor, though PIC24, MSP430 and AVR customizations are included in the distribution.
     
    The caution about non-atomic memory incrementation does apply, though, if you are out of the bottom 8K of RAM.  Which, in most simple embedded systems isn't likely.


    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #8
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2017/05/13 18:51:58 (permalink)
    4 (2)
    picmadness
    I don't think the PIC24 has a MMU or kernelspace/user space - how can you implement a RTOS? I guess as long as the software behaves it would work.

    No, there's no MMU etc., but that doesn't mean you can't implement an OS.  MMU, DAT and memory protection are all recent additions, lots of OS's were written before they showed up on the scene.
     
    In an embedded system it is assumed the software will behave.  The company selling the product is the one responsible for the software; the product's user doesn't get to write software for it.

    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #9
    NorthGuy
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    Re: A minimalist RTOS for the PIC24 2017/05/13 21:19:58 (permalink)
    3.5 (2)
    Nicholas Lindan
    The caution about non-atomic memory incrementation does apply, though, if you are out of the bottom 8K of RAM. 


    Not really. You just need to use different instructions with register addressing.


    #10
    nbiswas.iitk
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    Re: A minimalist RTOS for the PIC24 2017/05/14 13:10:56 (permalink)
    0
    Any chance for PIC18 XC8 ?
    #11
    Aussie Susan
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    Re: A minimalist RTOS for the PIC24 2017/05/14 20:09:57 (permalink)
    4 (1)
    nbiswas.iitk
    Any chance for PIC18 XC8 ?

    Can you please explain what this means?
    XC8 already creates code for the PIC18 families. Or do you mean an RTOS for the PIC18 families that can be compiled by the XC8 compiler?
    Also questions related to the XC8 compiler should probably be addressed in the XC8 forum.
    Susan
    post edited by Aussie Susan - 2017/05/14 20:10:58
    #12
    CinziaG
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    Re: A minimalist RTOS for the PIC24 2017/05/15 01:29:43 (permalink)
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    Aussie Susan
    Or do you mean an RTOS for the PIC18 families that can be compiled by the XC8 compiler?
     



    Yeah, I guessed that Smile

    mi fate schifo, umani di merda.
    #13
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2017/05/15 14:35:42 (permalink)
    3 (1)
    nbiswas.iitk
    Any chance for PIC18 XC8 ?

    Not planning any support for the PIC18.  That doesn't mean you can't modify the code to run on this processor - but it may be a struggle what with the PIC18's small hardware stack and paged memory.
     
    There are RTOS's that claim support for the PIC18, google for a smorgasbord.  I am not familiar enough with any of them to make a recommendation.
     
    I wrote an RTOS for the i8031 that rolled the stack in and out of external RAM on context switches.  Not the most appetizing of solutions.  The system had a large number of tasks and the limited internal RAM couldn't be divided into that many stacks each of the required size.

    Nicholas Lindan
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    #14
    Barbiani
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    Re: A minimalist RTOS for the PIC24 2017/05/15 17:23:35 (permalink)
    0
    what about pic32?
    #15
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2018/01/19 12:32:57 (permalink)
    0
    V1c is released.  This is an edit to the documentation and module comments.
     
    There are no plans for a PIC32 version.  Applications where a MIPS processors is appropriate aren't what one would call "minimalist."  A preemptive OS might be more appropriate.  There is nothing that precludes CoRTOS from being ported to a PIC32/MIPS; a user on AVRFreaks has ported it to the ARM Cortex M0 architecture.
     
     

    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #16
    Nicholas Lindan
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    Re: A minimalist RTOS for the PIC24 2018/05/16 05:37:04 (permalink)
    3 (1)
    Version 1d is released.  Changes are:
    • Fewer files, but with conditional compilation for various procesors
    • Added support for Cortex M0+
     

    Nicholas Lindan
    Cleveland Engineering Design, LLC
    #17
    marcov
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    Re: A minimalist RTOS for the PIC24 2018/07/25 09:07:30 (permalink)
    0
    @qhb:
     
    Preemptive is a way of making the timeslicer elongate timeslices if not many other tasks are available. This optimizes throughput, but reduces latency (since the next scheduler poll will only be when the longer timeslice finishes)
     
    At school we first had to build a simple round robin timeslicer for a 8051 clone (Hitachi 80515), and then expand it to preemptive to optimize throughput. The changes were quite slight.
     
     
     
    #18
    jack@kksound
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    Re: A minimalist RTOS for the PIC24 2018/07/25 09:46:28 (permalink)
    0
    Preemptive is a way of making the timeslicer elongate timeslices if not many other tasks are available. This optimizes throughput, but reduces latency (since the next scheduler poll will only be when the longer timeslice finishes)

    I think you mean that the longer timeslices INCREASE latency, not reduce latency. 
    #19
    JorgeF
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    Re: A minimalist RTOS for the PIC24 2018/07/25 11:53:06 (permalink)
    0
    Hi
    jack@kksound
    Preemptive is a way of making the timeslicer elongate timeslices if not many other tasks are available. This optimizes throughput, but reduces latency (since the next scheduler poll will only be when the longer timeslice finishes)

    I think you mean that the longer timeslices INCREASE latency, not reduce latency. 



    Maybe more time slices in a row, not longer.
    Its what happens when the ready list as only one task. The scheduler can even skip the save/restore context sequence because its returning to the same task (preempted or cooperative).

    Best regards
    Jorge
     
    I'm here http://picforum.ric323.com too!
    And it works better....
    #20
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