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Helpful ReplyHot!Solved: can't get PWM to control pins

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MachineMaker
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2016/11/27 11:33:31 (permalink)
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Solved: can't get PWM to control pins

Final: I had somehow missed the FLCONx FLTMOD bits, which default to latching fault. Something, somewhere else, has a default of causing a fault. (I'm sure I'll find out what, eventually.) Not sure why, but the PWM, when enabled in a fault condition, didn't take ownership of the pins, leaving them as GPIO. That really confused the heck out of me. Once the fault input was disabled (FLTMOD = 3), the PWM worked as expected. Much thanks to Stampede for the help.
 
Update: found writing to the latch still controls the pins. Can't get the pwm to take control. See my last message.


I'm on a dsPIC33EP64GS506, current MPLAB X, and I'm having PWM trouble.  I can get the right frequency out of the PWM sync output (PTCONbits.SYNCOEN, mapped to RB1, pin 28), so I conclude the Aux PLL is good, but I can't get anything on any pins for PWM1 and PWM2, not even with override.  (Goal is a full bridge.)  JTAG is off.  TRIS registers are set to outputs.  Debug build or not.  Followed the Errata for the PWM ... nada.  I'm baffled.  Any ideas?  Thank you! I'd attach some files but they're heavy with my personal notes in comments, but here's some excerpts that might help: ACLKCONbits.FRCSEL = 1; // select FRC as source for aux PLL
ACLKCONbits.SELACLK = 1; // aux oscillator provides clock source
ACLKCONbits.APSTSCLR = 7; // divide aux clock by 1
ACLKCONbits.ENAPLL = 1; // enable aux PLL
//while (ACLKCONbits.APLLCK != 1); // wait for PLL lock
__delay32( (unsigned long)2500 );
// NEXT, the PWMs
PWMCON1bits.IUE = 0; // Disable immediate update of duty cycle
PWMCON2bits.IUE = 0;
PWMCON1bits.ITB = 0; // Use PTPER
PWMCON2bits.ITB = 0;
PWMCON1bits.MTBS = 0; // Use Primary Master time base
PWMCON2bits.MTBS = 0;
PWMCON1bits.MDCS = 1; // MDC provides duty cycle value
PWMCON2bits.MDCS = 1;
RPOR0bits.RP33R = 0b101101; // Assign SYNCO to RP33, Pin 28
TRISBbits.TRISB1 = 0; // Make RB1, pin 28, an output
PTCONbits.SYNCOEN = 1; // Enable SYNCO output
PTPER = 23918; // PWM master period
STPER = 23918; // ( 119.632 MHz * 8 * 25µs / 1 ) - 8 = 23,918.4
MDC = 11959; // PWM master duty cycle
// ( 119.632 MHz * 8 * 12.5us / 1 ) = value)
// minimum is 0x0008, maximum is (period + 0x0008)
// can go less or more, just goes to min and max
// bit resolution = 14 bits = log2 x (119.632 x 8 x 25µs / 1) = 14.54631572281727
PDC1 = 11959;
DTR1 = 0; // dead time ( 119.632 MHz x 8 x 5ns / 1 ) = 4.785
ALTDTR1 = 0; // see pic "Dead Time.png" on desktop
DTR2 = 0;
ALTDTR2 = 0;
// MOTOR CONTROL / INDUCTIVE LOAD
IOCON1bits.CLDAT1 = 0; // Current limit turns on low sides for
IOCON1bits.CLDAT0 = 1; // recirculating inductive current
IOCON2bits.CLDAT1 = 0;
IOCON2bits.CLDAT0 = 1;
// Current limit
FCLCON1bits.CLMOD = 0; // Current limit mode enable (1) or disable (0)
// PWMCAP1 gets period register at current limit rising edge.
// default is 0
// TRIG1 = 0; // HIGH side ADC is triggered when PWM
// STRIG1 = 0; // LOW side Master matches this value
// **************************
// Per Errata on 3/14/2016...
// **************************
// 1.
// Make inputs to avoid glitch when enabling
TRISAbits.TRISA3 = 1;
TRISAbits.TRISA4 = 1;
TRISBbits.TRISB13 = 1;
TRISBbits.TRISB14 = 1;
// 2.
// GPIO controls pins, not PWM
IOCON1bits.PENH = 0;
IOCON1bits.PENL = 0;
IOCON2bits.PENH = 0;
IOCON2bits.PENL = 0;
// 3.
// When PWM outputs are overridden, High is off, and Low is on
IOCON1bits.OVRDAT1 = 0; // PWM1 H, pin 2
IOCON1bits.OVRDAT0 = 1; // PWM1 L, pin 3
IOCON2bits.OVRDAT1 = 0; // PWM2 H, pin 62
IOCON2bits.OVRDAT0 = 1; // PWM2 L, pin 63
// 4.
IOCON2bits.OVRENH = 1; // override PWM output with OVRDAT1
IOCON2bits.OVRENL = 1; // override PWM output with OVRDAT0
IOCON1bits.OVRENH = 1; // 0 = PWM supplies pin state
IOCON1bits.OVRENL = 1; // 1 = Override supplies pin state
// IOCON1bits.PMOD default is complementary, 0b00, 0
// complementary mode: L OR H, not AND, not NOR
// 5.
// PWM enabled
PTCONbits.PTEN = 1;
// 6.
IOCON2bits.OVRENH = 0; // override PWM output with OVRDAT1
IOCON2bits.OVRENL = 0; // override PWM output with OVRDAT0
IOCON1bits.OVRENH = 0; // 0 = PWM supplies pin data
IOCON1bits.OVRENL = 0;
// 7.
// 50 MHz instr clock cycle, delay for 1 PWM cycle of 40kHz
__delay32( (unsigned long)1250 );
// 8.
// PWM controls pins, not GPIO
IOCON1bits.PENH = 1;
IOCON1bits.PENL = 1;
IOCON2bits.PENH = 1;
IOCON2bits.PENL = 1;
// 9. (implied?))
TRISAbits.TRISA3 = 0; // pin 3, PWM 1 low
TRISAbits.TRISA4 = 0; // pin 2, PWM 1 high
TRISBbits.TRISB13 = 0; // pin 62, PWM 2 high
TRISBbits.TRISB14 = 0; // pin 63, PWM 2 low **************************************************************************************** // I might not have kept all the comments up with the existing switch settings// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Boot Segment Flash page address limit)// FSIGN// FOSCSEL
#pragma config FNOSC = FRCPLL // Oscillator Source Selection (Fast RC Oscillator with divide-by-N with PLL module (FRCPLL) )
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up with user-selected oscillator source)// FOSC
#pragma config POSCMD = NONE // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config IOL1WAY = OFF // Peripheral pin select configuration bit (Allow only one reconfiguration)
#pragma config FCKSM = CSDCMD // Clock Switching Mode bits (Clock switching is enabled, and Fail-safe Clock Monitor is disabled)
#pragma config PLLKEN = ON // PLL Lock Enable Bit (Clock switch to PLL source will wait until the PLL lock signal is valid)// FWDT
#pragma config WDTPOST = PS32768 // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128 // Watchdog Timer Prescaler bit (1:128)
#pragma config WDTEN = OFF // Watchdog Timer Enable bits (WDT and SWDTEN disabled)
#pragma config WINDIS = OFF // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)// FPOR// FICD
#pragma config ICS = PGD3 // DEBUGGING!! ICD Communication Channel Select bits (Communicate on PGEC3 and PGED3)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)
#pragma config BTSWP = OFF // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)// FDEVOPT
#pragma config PWMLOCK = OFF // PWMx Lock Enable bit (PWM registers may be written without key sequence)
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config DBCC = OFF // DACx Output Cross Connection bit (No Cross Connection between DAC outputs)// FALTREG
#pragma config CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)// FBTSEQ
#pragma config BSEQ = 0xFFF // Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active (Boot Sequence Number bits)
#pragma config IBSEQ = 0xFFF // The one's complement of BSEQ; must be calculated by the user and written during device programming. (Inverse Boot Sequence Number bits)
post edited by MachineMaker - 2016/11/29 15:57:57
#1
Stampede
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Re: PWM sync out is good, but pins are silent 2016/11/28 04:48:34 (permalink)
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Did you set/reset the fuse to reconfig the PWM IOs properly? Cleared all fault conditions?
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MachineMaker
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Re: PWM sync out is good, but pins are silent 2016/11/28 15:36:41 (permalink)
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Thank you for your help so far, Stampede.
 
The faults default to disabled, and none are triggered.
 
I don't know what "set/reset the fuse to reconfig the PWM IOs properly" means. Fuse? What is the proper way to reconfigure PWM IOs?  I have a feeling this is it, whatever it is.  Though I've tried setting and clearing the IOCONxbits.PENH/L bits, which are supposed to control pin ownership, the PWM never takes control of the pin.  (As I've recently discovered,) the GPIO controls the pin no matter what I do.  Why?
post edited by MachineMaker - 2016/11/28 15:37:57
#3
Stampede
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Re: PWM sync out is good, but pins are silent 2016/11/29 01:51:07 (permalink) ☄ Helpfulby MachineMaker 2016/11/29 15:47:24
4.33 (3)
Hi,
 
This is wrong. 0 ist not allowed. 3 Disables the fault. I cant see that in your config:
// Current limit
FCLCON1bits.CLMOD = 0; // Current limit mode enable (1) or disable (0)
 
This is what I do (any it works):

    /* Initialize Period */
    PTPER = PSFBPWMPeriod;          // Main period for PWM switching
    BUCK_PERIOD_REG = BUCKPWMPERIOD;          // period for buck converter
    PDC1 = PSFBHalfPeriod ;
    PDC2 = PSFBHalfPeriod ;
    PTCONbits.EIPU = 0;
    STCONbits.EIPU = 0;
    
    FCLCON1 = 0;
    FCLCON2 = 0;
    FCLCON3 = 0;
    FCLCON4 = 0;
    FCLCON5 = 0;
    
    // Clear Config Structure
    IOCON1 = 0;
    IOCON2 = 0;
    IOCON3 = 0;
    IOCON4 = 0;
    IOCON5 = 0;
    
    /*Initialization of the PWM1 for the left leg*/        
    #ifdef APPLY_PWM_GLITCH_ERRATA
        TRISAbits.TRISA4 = 1;   // Configure PWM1H/RA4 as digital input
                                // Ensure output is in safe state using pull-up or pull-down resistors
        TRISAbits.TRISA3 = 1;   // Configure PWM1L/RA3 as digital input
                                // Ensure output is in safe state using pull-up or pull-down resistors
        IOCON1bits.PENH = 0;   // Assign pin ownership of PWM1H/RA4 to GPIO module
        IOCON1bits.PENL = 0;   // Assign pin ownership of PWM1L/RA3 to GPIO module
        IOCON1bits.OVRDAT = 0; // Configure PWM outputs override state to the desired safe state
        IOCON1bits.OVRENH = 1; // Override PWM1H output
        IOCON1bits.OVRENL = 1; // Override PWM1L output   
    #endif
    // PWM1 Configuration
    IOCON1bits.POLH = 0;       // PWM Output Polarity is high
    IOCON1bits.POLL = 0;       // PWM Output Polarity is high
    IOCON1bits.PMOD = 0;       // PWM I/O pin pair is in the Complementary Output mode
    IOCON1bits.OSYNC = 0;      // 0 = Output overrides via the OVRDAT<1:0> bits occur on the next CPU clock boundary
                                // 1 = Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
    PWMCON1bits.ITB = 0;        // PTPER register provides timing for this PWM generator
    PWMCON1bits.MDCS = 0;       // PDCx (and SDCx) registers provide duty cycle information for this PWMx generator
    PWMCON1bits.DTC = 0;        // Positive dead time is actively applied for all Output modes
    PWMCON1bits.IUE = 0;        // Updates are synchronized to the local PWMx time base
    DTR1    = PSFBDEADTIME_VAL;     // Dead time setting
    ALTDTR1 = PSFBALTDEADTIME_VAL;  // Dead time setting
    PHASE1 = 0;                 // Do not shift PWM1

 
    /* Prim Side Fault */
    mDEASSERT_PWM_FAULT();
    FCLCON1bits.FLTSRC = FLTSRC_FAULT11;   // FLT11 has been selected for the Fault control signal source for PWM Generator3
    FCLCON2bits.FLTSRC = FLTSRC_FAULT11;   // FLT11 has been selected for the Fault control signal source for PWM Generator4     
    FCLCON1bits.FLTPOL = 0;    // The selected Fault source is active-high
    FCLCON2bits.FLTPOL = 0;    // The selected Fault source is active-high
    FCLCON1bits.FLTMOD = FLT_MODE_FLTDATX_CYCLE;    // 3: OFF, 1: The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
    FCLCON2bits.FLTMOD = FLT_MODE_FLTDATX_CYCLE;    // 3: OFF, 1: The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
    FCLCON1bits.IFLTMOD = 0;   // Normal Fault mode
    FCLCON2bits.IFLTMOD = 0;   // Normal Fault mode
    IOCON1bits.FLTDAT = 0;     // Set PWMxH/L low in case of a fault
    IOCON2bits.FLTDAT = 0;     // Set PWMxH/L low in case of a fault 

 
[...]
 

#4
MachineMaker
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Re: PWM sync out is good, but pins are silent 2016/11/29 15:46:48 (permalink)
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Stampede, thank you so much for your help. I've been beating my head against the wall for days.
 
I think when you saw CLMOD you recognized it as FLTMOD, which needs 3 to be disabled ... and which I had completely overlooked, somehow. That was what I was missing. Now it works. FINALLY.
 
Just for curiosity, after setting FLTMOD to 3, I enabled the fault interrupt and immediately received the fault flag. Not sure what's causing a fault yet, or why. The dsPIC is a lot more to learn than the 18. Thank you again for your patience and help.
#5
mahendraware
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Re: Solved: can't get PWM to control pins 2018/02/18 22:11:32 (permalink)
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Hello
I am using this code to generate the PWM using dsPIC33EP256GP506 DSC . I am getting lots of errors related to
IOCON1bits
ADCONbits
IFS0bits
PWMCON1bits
Is there any file is missing in my project. Please help me out.
 
Thanks & Regards,
Mahendra Ware
#6
snellr314
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Re: Solved: can't get PWM to control pins 2019/01/18 13:09:52 (permalink)
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My project has "#include "xc.h"" (which points back to my device specific header file) and then I use PG1IOCONHbits.whatever
I think there is a different library, perhaps libc30 being used by the previous poster.
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