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Answeredv3 Not setting UART Baudrate correctly?

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Nikel
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2016/05/05 07:56:18 (permalink)
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v3 Not setting UART Baudrate correctly?

Hi, I'm using a PIC18F46K22 and CC v3. I've set system clock to Internal oscillator, FOSC, 16MHz_HFINTOSC/4 (4xPLL enabled giving 64MHz). I then configured UART1 module with CC to 57600 baudrate and generated the code, but the real communication baudrate when running is 14400 (56700/4, that is). So, is CC setting this wrong (doing the math wrong) or am I missing something?
 
Thank you.
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SorinV
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Re: v3 Not setting UART Baudrate correctly? 2016/05/06 01:50:43 (permalink)
5 (1)
Hi Nikel,

I just checked the registers settings. 
According to the datasheet if you followed your settings you would be in the highlighted case bellow.
 
With the SPBRGH1:SPBRG1 set to 0x115 the baudrate would be: 57553.9568345. (this is for the current version we are working on right now. If one of the settings you are using does not match the values in the table above and the ones for USART registers then this is the problem you are facing)

Without further information from you I would say that this issue if present in the current official version of MCC v3 will be fixed in the next release.

Let me know if I can further assist you in debugging your code and finally make it work if you don't want to wait for the release. If so please send if possible pictures and mcc config file.

regards
Sorin
 
post edited by SorinV - 2016/05/06 05:47:08

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Nikel
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Re: v3 Not setting UART Baudrate correctly? 2016/05/06 06:51:18 (permalink)
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Yes, sorry about that, I don't know why I didn't copy the generated code!
// CONFIG1H
#pragma config FOSC = INTIO67 // Oscillator Selection bits->Internal oscillator block
#pragma config PLLCFG = ON // 4X PLL Enable->Oscillator multiplied by 4
#pragma config PRICLKEN = ON // Primary clock enable bit->Primary clock is always enabled
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit->Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit->Oscillator Switchover mode disabled
 
void OSCILLATOR_Initialize(void)
{
    // SCS FOSC; IRCF 16MHz_HFINTOSC/4; IDLEN disabled;
    OSCCON = 0x70;
    // PRISD enabled; SOSCGO disabled; MFIOSEL disabled;
    OSCCON2 = 0x04;
    // INTSRC disabled; PLLEN disabled; TUN 0;
    OSCTUNE = 0x00;
    // Set the secondary oscillator
}
 
void EUSART1_Initialize(void)
{
    // disable interrupts before changing states
    PIE1bits.RC1IE = 0;
    PIE1bits.TX1IE = 0;
    // Set the EUSART1 module to the options selected in the user interface.
    // ABDOVF no_overflow; CKTXP async_noninverted_sync_fallingedge; BRG16 16bit_generator; WUE disabled; ABDEN disabled; DTRXP not_inverted;
    BAUDCON1 = 0x08;
    // SPEN enabled; RX9 8-bit; CREN enabled; ADDEN disabled; SREN disabled;
    RCSTA1 = 0x90;
    // TX9 8-bit; TX9D 0; SENDB sync_break_complete; TXEN enabled; SYNC asynchronous; BRGH hi_speed; CSRC slave_mode;
    TXSTA1 = 0x24;
    // Baud Rate = 57600;
    SPBRG1 = 0x15;
    // Baud Rate = 57600;
    SPBRGH1 = 0x01;
    
    // initializing the driver state
    eusart1TxHead = 0;
    eusart1TxTail = 0;
    eusart1TxBufferRemaining = sizeof(eusart1TxBuffer);
    eusart1RxHead = 0;
    eusart1RxTail = 0;
    eusart1RxCount = 0;
    // enable receive interrupt
    PIE1bits.RC1IE = 1;
}
So SPBRGH1:SPBRG1 is set to 0x115, yet the real baudrate is 14400...?
 
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argogee2015
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Re: v3 Not setting UART Baudrate correctly? 2016/05/06 07:28:23 (permalink) ☼ Best Answerby SorinV 2016/05/08 23:41:32
4.5 (2)
Nikel
Yes, sorry about that, I don't know why I didn't copy the generated code!
// CONFIG1H
 
#pragma config FOSC = INTIO67 // Oscillator Selection bits->Internal oscillator block
#pragma config PLLCFG = ON // 4X PLL Enable->Oscillator multiplied by 4
#pragma config PRICLKEN = ON // Primary clock enable bit->Primary clock is always enabled
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit->Fail-Safe Clock Monitor disabled
#pragma config IESO = OFF // Internal/External Oscillator Switchover bit->Oscillator Switchover mode disabled
 
 
 
void OSCILLATOR_Initialize(void)
{
 
    // SCS FOSC; IRCF 16MHz_HFINTOSC/4; IDLEN disabled;
 
    OSCCON = 0x70;
 
    // PRISD enabled; SOSCGO disabled; MFIOSEL disabled;
 
    OSCCON2 = 0x04;
 
    // INTSRC disabled; PLLEN disabled; TUN 0;
 
    OSCTUNE = 0x00;
 
    // Set the secondary oscillator
}


Datasheet page 39/560.  2.8.2 PLL IN HFINTOSC MODES
Unlike external clock modes, when internal clock
modes are enabled, the PLL can only be controlled
through software. The PLLEN control bit of the
OSCTUNE register is used to enable or disable the
PLL operation when the HFINTOSC is used.
 
Check the frequency, I think it is 16MHz according to the codes you pasted.
Fosc=16000000
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SorinV
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Re: v3 Not setting UART Baudrate correctly? 2016/05/06 07:53:04 (permalink)
4.5 (2)
Nikel
So SPBRGH1:SPBRG1 is set to 0x115, yet the real baudrate is 14400...?



I can confirm a baudrate of 14467.
 
And we also found the problem.

So. If you check the datasheet you can see that the PLLCFG config bit is available only for external oscillators.

So the clock you use is still 16MHz. In  order to use PLL with internal oscilator you should check the Software PLL enabled in MCC or the PLLEN bit from OSCTUNE register. (same thing)

This would be your fix.

We acknowledged the issue and we will fix it by the next release.
Thank you for this helpful report.

Have a nice day!
Sorin
post edited by SorinV - 2016/05/06 07:59:50
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Nikel
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Re: v3 Not setting UART Baudrate correctly? 2016/05/06 08:08:06 (permalink)
0
Great! Thank you for your help! And I'm happy to have helped clear this out.
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