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Hot!PIC32MZ2048EFH100 oscillator problem

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Variszabi
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2016/02/26 16:00:37 (permalink)
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PIC32MZ2048EFH100 oscillator problem

Hello!
 
I ran into a problem with the PIC32MZ2048EFH100 MCU.
I would like to use with this oscillator:
The oscillator output is connected to OSCI and OSCI left open.
The problem is that, I would like to 200MHz but the PIC is running at 8MHZ backup oscillator.
 
The configuration bits are following:
// DEVCFG3
// USERID = No Setting
#pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled)
#pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)
#pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration)
#pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)
#pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)
#pragma config FUSBIDIO = ON // USB USBID Selection (Controlled by the USB Module)

// DEVCFG2
#pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)
#pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
#pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)
#pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
#pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
#pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)

// DEVCFG1
#pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
#pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
#pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable SOSC)
#pragma config IESO = ON // Internal/External Switch Over (Enabled)
#pragma config POSCMOD = HS // Primary Oscillator Configuration (HS osc mode)
#pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
#pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
#pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
#pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
#pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
#pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
#pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
#pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
#pragma config FDMTEN = ON // Deadman Timer Enable (Deadman Timer is enabled)

// DEVCFG0
#pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)
#pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
#pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
#pragma config TRCEN = ON // Trace Enable (Trace features in the CPU are enabled)
#pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
#pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
#pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
#pragma config DBGPER = ALLOW_PG2 // Debug Mode CPU Access Permission (Allow CPU access to Permission Group 2 permission regions)
#pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
#pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
#pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
#pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
#pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)

// DEVCP0
#pragma config CP = OFF // Code Protect (Protection Disabled)

// SEQ3

 
Frequency check in the main is the following:
int main(int argc, char** argv) {

init_io();
_CP0_SET_COUNT(0);

while(_CP0_GET_COUNT() < 100000000);
PORTDbits.RD1 = 1;

while(1)
{
;
}
return 0;
}

 
The LED at the RD1 is loght up 25s after start. It means that (100000000 / 25) * 2 = 8000000 Hz
#1

15 Replies Related Threads

    RISC
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 16:07:30 (permalink)
    3 (1)
    Hi,
    Please check carfully the deadtime timer...You should probably set it to off
    Regards
    #2
    Variszabi
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 16:16:29 (permalink)
    0
    Where I can find the deadtime timer settings?
    I never heard about it. :) Or did you mean as deadman timer?
    post edited by Variszabi - 2016/02/26 16:22:17
    #3
    DarioG
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 16:46:27 (permalink)
    0
    Also, write to LATx, generally speaking :)

    GENOVA :D :D ! GODO
    #4
    Variszabi
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 16:52:33 (permalink)
    0
    So the Deadman Timer is turned off and write to LATx, but the problem is same.
    Here is the new configuration:
     
    // DEVCFG3
    // USERID = No Setting
    #pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled)
    #pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)
    #pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration)
    #pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)
    #pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)
    #pragma config FUSBIDIO = ON // USB USBID Selection (Controlled by the USB Module)

    // DEVCFG2
    #pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)
    #pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
    #pragma config FPLLICLK = PLL_POSC // System PLL Input Clock Selection (POSC is input to the System PLL)
    #pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
    #pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
    #pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)

    // DEVCFG1
    #pragma config FNOSC = SPLL // Oscillator Selection Bits (System PLL)
    #pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
    #pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable SOSC)
    #pragma config IESO = ON // Internal/External Switch Over (Enabled)
    #pragma config POSCMOD = HS // Primary Oscillator Configuration (HS osc mode)
    #pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
    #pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
    #pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
    #pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
    #pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
    #pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
    #pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
    #pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
    #pragma config FDMTEN = OFF // Deadman Timer Disable (Deadman Timer is disabled)

    // DEVCFG0
    #pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)
    #pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
    #pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
    #pragma config TRCEN = ON // Trace Enable (Trace features in the CPU are enabled)
    #pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
    #pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
    #pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
    #pragma config DBGPER = ALLOW_PG2 // Debug Mode CPU Access Permission (Allow CPU access to Permission Group 2 permission regions)
    #pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
    #pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
    #pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
    #pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
    #pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
    #pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)

    // DEVCP0
    #pragma config CP = OFF // Code Protect (Protection Disabled)

    #5
    NorthGuy
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 17:57:24 (permalink)
    0
    You didn't really say what oscillator you use.
     
    Errata says that crystal oscillator doesn't work (e.g. POSCMOD = HS) and suggests using EC instead.
    #6
    simong123
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 18:11:27 (permalink)
    3 (1)
    Variszabi
    The oscillator output is connected to OSCI and OSCI left open.

    I presume you mean
    The oscillator output is connected to OSCI (pin 49) and OSCO (pin 50) left open.
     
    In which case

    #pragma config POSCMOD = HS // Primary Oscillator Configuration (HS osc mode)

    is wrong. Should be

    #pragma config POSCMOD = EC             // Primary Oscillator Configuration (External clock mode)

     
    Without knowing your oscillator speed, it is impossible to verify your other settings, but they look correct for a 24MHz oscillator.
    #7
    Variszabi
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 18:27:26 (permalink)
    0
    Thank you, I have replaced the HS with EC.
    And the PLL is not working too. But now I have tried to select the POSC as input oscillator and the MCU running at 24MHz. But when I select FPLLICLK as POSC and FNOSC as PLL it will runing at 8MHz backup timer. The PLL is not working. When I try to start the PLL from FRC it is not working too.
     
    // PIC32MZ2048EFH100 Configuration Bit Settings
    // 'C' source line config statements
    #include <xc.h>
    // DEVCFG3
    // USERID = No Setting
    #pragma config FMIIEN = ON // Ethernet RMII/MII Enable (MII Enabled)
    #pragma config FETHIO = ON // Ethernet I/O Pin Select (Default Ethernet I/O)
    #pragma config PGL1WAY = ON // Permission Group Lock One Way Configuration (Allow only one reconfiguration)
    #pragma config PMDL1WAY = ON // Peripheral Module Disable Configuration (Allow only one reconfiguration)
    #pragma config IOL1WAY = ON // Peripheral Pin Select Configuration (Allow only one reconfiguration)
    #pragma config FUSBIDIO = OFF // USB USBID Selection (Controlled by Port Function)
    // DEVCFG2
    #pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (1x Divider)
    #pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
    #pragma config FPLLICLK = PLL_FRC // System PLL Input Clock Selection (FRC is input to the System PLL)
    #pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
    #pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)
    #pragma config UPLLFSEL = FREQ_24MHZ // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)
    // DEVCFG1
    #pragma config FNOSC = POSC // Oscillator Selection Bits (Primary Osc (HS,EC))
    #pragma config DMTINTV = WIN_127_128 // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
    #pragma config FSOSCEN = OFF // Secondary Oscillator Enable (Disable SOSC)
    #pragma config IESO = ON // Internal/External Switch Over (Enabled)
    #pragma config POSCMOD = EC // Primary Oscillator Configuration (HS osc mode)
    #pragma config OSCIOFNC = OFF // CLKO Output Signal Active on the OSCO Pin (Disabled)
    #pragma config FCKSM = CSECME // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Enabled)
    #pragma config WDTPS = PS1048576 // Watchdog Timer Postscaler (1:1048576)
    #pragma config WDTSPGM = STOP // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
    #pragma config WINDIS = NORMAL // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
    #pragma config FWDTEN = OFF // Watchdog Timer Enable (WDT Disabled)
    #pragma config FWDTWINSZ = WINSZ_25 // Watchdog Timer Window Size (Window size is 25%)
    #pragma config DMTCNT = DMT31 // Deadman Timer Count Selection (2^31 (2147483648))
    #pragma config FDMTEN = OFF // Deadman Timer Enable (Deadman Timer is disabled)
    // DEVCFG0
    #pragma config DEBUG = OFF // Background Debugger Enable (Debugger is disabled)
    #pragma config JTAGEN = OFF // JTAG Enable (JTAG Disabled)
    #pragma config ICESEL = ICS_PGx1 // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
    #pragma config TRCEN = ON // Trace Enable (Trace features in the CPU are enabled)
    #pragma config BOOTISA = MIPS32 // Boot ISA Selection (Boot code and Exception code is MIPS32)
    #pragma config FECCCON = OFF_UNLOCKED // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
    #pragma config FSLEEP = OFF // Flash Sleep Mode (Flash is powered down when the device is in Sleep mode)
    #pragma config DBGPER = ALLOW_PG2 // Debug Mode CPU Access Permission (Allow CPU access to Permission Group 2 permission regions)
    #pragma config SMCLR = MCLR_NORM // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
    #pragma config SOSCGAIN = GAIN_2X // Secondary Oscillator Gain Control bits (2x gain setting)
    #pragma config SOSCBOOST = ON // Secondary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
    #pragma config POSCGAIN = GAIN_2X // Primary Oscillator Gain Control bits (2x gain setting)
    #pragma config POSCBOOST = ON // Primary Oscillator Boost Kick Start Enable bit (Boost the kick start of the oscillator)
    #pragma config EJTAGBEN = NORMAL // EJTAG Boot (Normal EJTAG functionality)
    // DEVCP0
    #pragma config CP = OFF // Code Protect (Protection Disabled)
    // SEQ3

    #8
    simong123
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 19:08:18 (permalink)
    0
    These are my working settings for a 24MHz oscillator input for a 200MHz sysclk:

    // DEVCFG3
    // USERID = No Setting
    #pragma config FMIIEN = OFF             // Ethernet RMII/MII Enable (RMII Enabled)
    #pragma config FETHIO = ON              // Ethernet I/O Pin Select (Default Ethernet I/O)
    #pragma config PGL1WAY = OFF            // Permission Group Lock One Way Configuration (Allow multiple reconfigurations)
    #pragma config PMDL1WAY = OFF           // Peripheral Module Disable Configuration (Allow multiple reconfigurations)
    #pragma config IOL1WAY = OFF            // Peripheral Pin Select Configuration (Allow multiple reconfigurations)
    #pragma config FUSBIDIO = ON            // USB USBID Selection (Controlled by the USB Module)

    // DEVCFG2
    #pragma config FPLLIDIV = DIV_3         // System PLL Input Divider (3x Divider)
    #pragma config FPLLRNG = RANGE_8_16_MHZ // System PLL Input Range (8-16 MHz Input)
    #pragma config FPLLICLK = PLL_POSC      // System PLL Input Clock Selection (POSC is input to the System PLL)
    #pragma config FPLLMULT = MUL_50        // System PLL Multiplier (PLL Multiply by 50)
    #pragma config FPLLODIV = DIV_2         // System PLL Output Clock Divider (2x Divider)
    #pragma config UPLLFSEL = FREQ_24MHZ    // USB PLL Input Frequency Selection (USB PLL input is 24 MHz)

    // DEVCFG1
    #pragma config FNOSC = SPLL             // Oscillator Selection Bits (System PLL)
    #pragma config DMTINTV = WIN_127_128    // DMT Count Window Interval (Window/Interval value is 127/128 counter value)
    #pragma config FSOSCEN = OFF            // Secondary Oscillator Enable (Disable SOSC)
    #pragma config IESO = ON                // Internal/External Switch Over (Enabled)
    #pragma config POSCMOD = EC             // Primary Oscillator Configuration (External clock mode)
    #pragma config OSCIOFNC = OFF           // CLKO Output Signal Active on the OSCO Pin (Disabled)
    #pragma config FCKSM = CSECMD           // Clock Switching and Monitor Selection (Clock Switch Enabled, FSCM Disabled)
    #pragma config WDTPS = PS1048576        // Watchdog Timer Postscaler (1:1048576)
    #pragma config WDTSPGM = STOP           // Watchdog Timer Stop During Flash Programming (WDT stops during Flash programming)
    #pragma config WINDIS = NORMAL          // Watchdog Timer Window Mode (Watchdog Timer is in non-Window mode)
    #pragma config FWDTEN = OFF             // Watchdog Timer Enable (WDT Disabled)
    #pragma config FWDTWINSZ = WINSZ_25     // Watchdog Timer Window Size (Window size is 25%)
    #pragma config DMTCNT = DMT31           // Deadman Timer Count Selection (2^31 (2147483648))
    #pragma config FDMTEN = OFF             // Deadman Timer Enable (Deadman Timer is disabled)

    // DEVCFG0
    #pragma config DEBUG = OFF              // Background Debugger Enable (Debugger is disabled)
    #pragma config JTAGEN = OFF             // JTAG Enable (JTAG Disabled)
    #pragma config ICESEL = ICS_PGx1        // ICE/ICD Comm Channel Select (Communicate on PGEC1/PGED1)
    #pragma config TRCEN = OFF              // Trace Enable (Trace features in the CPU are disabled)
    #pragma config BOOTISA = MIPS32         // Boot ISA Selection (Boot code and Exception code is MIPS32)
    #pragma config FECCCON = OFF_UNLOCKED   // Dynamic Flash ECC Configuration (ECC and Dynamic ECC are disabled (ECCCON bits are writable))
    #pragma config FSLEEP = VREGS           // Flash Sleep Mode (Flash power down is controlled by the VREGS bit)
    #pragma config DBGPER = PG_ALL       // Debug Mode CPU Access Permission (Allow CPU access to Permission Group 2 permission regions)
    #pragma config SMCLR = MCLR_NORM        // Soft Master Clear Enable bit (MCLR pin generates a normal system Reset)
    #pragma config SOSCGAIN = GAIN_2X       // Secondary Oscillator Gain Control bits (2x gain setting)
    #pragma config SOSCBOOST = OFF          // Secondary Oscillator Boost Kick Start Enable bit (Normal start of the oscillator)
    #pragma config POSCGAIN = GAIN_2X       // Primary Oscillator Gain Control bits (2x gain setting)
    #pragma config POSCBOOST = OFF          // Primary Oscillator Boost Kick Start Enable bit (Normal start of the oscillator)
    #pragma config EJTAGBEN = NORMAL        // EJTAG Boot (Normal EJTAG functionality)

     
    If these don't work, maybe it's time to check:-
    All VDD's connected and de-coupled (including AVDD) as per datasheet figure 2-1.
     
    #9
    NorthGuy
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 19:29:42 (permalink)
    4 (1)
    At these higher frequencies, decoupling capacitors are very important. I did an experiment, and I only was able to run it without decoupling capacitors at 40MHz. Even 50MHz was completely impossible to achieve. With decoupling capacitors, 200MHz wasn't a problem.
    #10
    Totem
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/26 22:52:53 (permalink)
    0
     
    Hi Variszabi,
     
    If you are using PLL make sure that the PLL settings are proper.
    This is what you are doing,
     
    #pragma config FPLLICLK = PLL_FRC // System PLL Input Clock Selection (FRC is input to the System PLL)
    //FRC is typically 8 MHz
    #pragma config FPLLIDIV = DIV_3 // System PLL Input Divider (3x Divider)
    //So, now the frequency is <3 MHz
    #pragma config FPLLRNG = RANGE_5_10_MHZ // System PLL Input Range (5-10 MHz Input)
    //These settings never work as you are feeding  <3 MHz to PLLMultiplier which is operating in 5 to 10 MHz range.
    #pragma config FPLLMULT = MUL_50 // System PLL Multiplier (PLL Multiply by 50)
    #pragma config FPLLODIV = DIV_2 // System PLL Output Clock Divider (2x Divider)


    To run device at 200 MHz using FRC you have to do following settings in PLL,
    #pragma config FPLLICLK = PLL_FRC
    //8 MHz
    #pragma config FPLLIDIV = DIV_1
    //8 MHz
    #pragma config FPLLRNG = RANGE_5_10_MHZ
    //Feeding right frequency
    #pragma config FPLLMULT = MUL_50
    //400 MHz
    #pragma config FPLLODIV = DIV_2
    //System clock is 200 MHz


    Select right PLL multiplier range(FPLLRNG) and feed right frequency by using correct value of FPLLDIV.

    I hope this helps you!
    post edited by Totem - 2016/02/26 23:52:14
    #11
    Variszabi
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/27 03:54:08 (permalink)
    4 (2)
    Thank you everybody for help!
    The problem was that one of Vdd PIN was not connected and de-coupled.
    Now the PLL is working and the PIN is OK. :)
    #12
    NorthGuy
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/27 08:28:13 (permalink)
    3 (1)
    Congratulations!
     
    @Totem: I think FIPLLDIV is ignored if the source is FRC. I noticed Harmony sets it to DIV_8 and it still works.
    #13
    Totem
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/27 22:27:45 (permalink)
    0
    I'm referring to the Datasheet,

    Whether it is POSC or FRC, PLL just considers it as clock source. 
    Am I missing anything?
    post edited by Totem - 2016/02/27 22:32:30

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    #14
    NorthGuy
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    Re: PIC32MZ2048EFH100 oscillator problem 2016/02/28 07:16:35 (permalink)
    0
    Totem
    Am I missing anything?



    Unfortunately, reality might be different from the diagrams from the datasheet. And that would make sense. Why use FIPLLDIV for FRC if any values except DIV_1 can only break it? Try it.
     
    Grau, theurer Freund, ist alle Theorie, Und grün des Lebens goldner Baum.
    #15
    Stri
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    Re: PIC32MZ2048EFH100 oscillator problem 2019/04/25 01:17:20 (permalink)
    0
    Had similar issue with my  PIC32MZ2048EFH100. My external clock was 50Mhz, and desired CPU freq was 250MHz (So I had div=1, MUL=10, ODiv=2 in CONFIG bits). Some chips worked without any problems, but some had very long start-up time (about 30sec or so). After reading datasheet one more time I found this note:
     
    Devices that support 252 MHz operation should be configured for SYSCLK <= 200 MHz operation. Adjust the dividers of the PBCLKs, and then increase the SYSCLK to the desired speed.
     
    And indeed, than I set my CONFIG bits to get 200Mhz PLL on power-up (div=1, MUL=8, ODiv=2), even those problematic MCU started to work properly. Hope it will be useful to someone...

    Let's telegram! t.me/microchip_forum
    #16
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