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Hot!dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution?

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Alec82
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2016/02/03 06:38:50 (permalink)
3 (1)

dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution?

Dear all!
 
I'm a little bit confused. PWM1 configured properly, runs, individual H/L have been set up, time base (PWM period) is checked by oscilloscope and is exactly the same I expected from the number I loaded to PHASE1 register. Aux clock is running on 120MHz, so this number is PHASE1=24038 for a 20kHz switching frequency, so I am OK. But just until this point...
 
When I load a number to SDC1 or PDC1 , I realize that the ratio of the number and 24038 gives the correct PWM duty cycle I want, but let's say the 3 LSB has absolutely no effect on duty cycle. For example, I load 1024 to SDC1 so the duty cycle is 1024/24038, and from a far view on the scope it is OK, but when I zoom on the falling edge (with a fixed trigger position which is out of the screen on the left) and change the SDC1 number to 1025 - 1026 - 1027 and so on until 1031 the position of the falling edge remains unchanged. When I load 1032 to SDC1 the falling edge jumps ~8ns to the right. This means 8 x 1.04ns resolution for me, so the real resolution is 8.32ns, instead.
 
What could be wrong? Am I missed something? All datasheet I read is talking about 1.04ns resolution, only the low end dsPICs of the GS serie has 8.32ns.
 
Could anyone measure 1.04ns real _resolution_ ? Is the 1.04ns only a hoax?
 
Thanks
#1

13 Replies Related Threads

    Mike017
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/03 19:01:25 (permalink)
    4 (1)
    Hi,
    What could be wrong? Am I missed something?
    Check you are not using Center Aligned mode or a prescaler other than 1:1.
     
    dsPIC33FJ64GS608
    Techtronix 2465B, 400MHz, auto-measuring pulse width (not me using the cursors):
    PDC5      Width
    10          10.67 ns    (very soft edges) 
    11          11.89
    12          12.96
    13          13.76
    1000      1.057 us    (nice edges)
    1001      1.058
    1002      1.059
    1003      1.061
    20000    21.15 us    (lost the third decimal point)
     
    Post back with config, oscillator and PWM settings if you still have trouble.
     
    Good Luck,
    Mike
     
     
    post edited by Mike017 - 2016/02/03 19:06:34
    #2
    Alec82
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/04 01:15:14 (permalink)
    0
    Hi Mike!
     
    Thank you for your answer. I copy the setup:
     
        ACLKCONbits.FRCSEL=1;
        ACLKCONbits.ENAPLL=1;
        ACLKCONbits.SELACLK=1;
        ACLKCONbits.APSTSCLR=7;
        while(ACLKCONbits.APLLCK!=1);    // AUX clk -> FRC (7.37MHz) * 16 (PLL) / postscaler (1:1) = 120MHz

        PTCONbits.PTEN=0;
        PTPER=48076;
        PTCONbits.SEIEN=0;
        PTCONbits.EIPU=0;
        PTCONbits.SYNCEN=0;
        PTCON2bits.PCLKDIV=0b000;
        PWMCON1bits.MDCS=0;
        PWMCON1bits.DTC=0b10;
        PWMCON1bits.IUE=0;
        IOCON1bits.PENL=1;
        IOCON1bits.PENH=1;
        IOCON1bits.PMOD=0b11;
        AUXCON1bits.HRPDIS=1;
        AUXCON1bits.HRDDIS=1;
        SDC1=0;
        PDC1=0;
        PHASE1=24038;


    Sorry, I wrote in my first post that the period was given by PHASE1, but PTPER=48076 makes the 50usec period, and PHASE1=24038 (half of PTPER) is only to make 180 degs phase shift between PWMH/L (PDC-SDC). And it is ok.
     
    I did not write anything to PWMCON1bits.CAM, because it is '0' by power up default, which means edge aligned mode, so no center align mode selected.
     
    With my config there is no center aligned mode, and if I'm right the clock divider is 1:1.
    Maybe there are unneccessary rows in my config, but they make no sense (for example write the same value to a bit as the power up default value).
     
    And of course, PTEN=1 goes after the config to turn on PWM.
     
    Could you please copy your config to compare?
    #3
    Alec82
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/04 02:06:39 (permalink)
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    Ah... I got the solution... I could say Mea Culpa, but maybe it is not only my fault (datasheet is not absolutely clear, and is short-spoken).
     
    So, in my config there is:
    AUXCON1bits.HRPDIS=1;
    AUXCON1bits.HRDDIS=1;
     
    I removed this two lines and voila, I got the 1.04ns resolution. By default these bits are '0', and I thougth that I need to set them '1' for high resolution PWM (as the datasheet says). These two bits are for something else (after this I don't really know what for, and from now I don't care), but I could not find any 'comment' in the datasheet about losing 3 LSB with these bits set. It says losing 3LSB is when I operate in center align mode and when I use duty cycle near 0% and 100%.
    #4
    davekw7x
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/04 11:44:33 (permalink)
    4 (1)
    DS70000591F (Emphasis added by davekw7x)
    10.4 PWM Power-Saving Features
    Typically, many applications need either a highresolution
    duty cycle or phase offset (for fixed
    frequency operation) or a high-resolution PWM period
    for variable frequency modes of operation (such as
    Resonant mode). Very few applications require both
    high-resolution modes simultaneously.
    The HRPDIS and the HRDDIS bits in the AUXCONx
    registers permit the user to disable the circuitry associated
    with the high-resolution duty cycle and PWM
    period to reduce the operating current of the device.
    If the HRDDIS bit is set, the circuitry associated with
    the high-resolution duty cycle, phase offset and dead
    time for the respective PWM generator, is disabled. If
    the HRPDIS bit is set, the circuitry associated with the
    high-resolution PWM period for the respective PWM
    generator is disabled.
    When the HRPDIS bit is set, the smallest unit of
    measure for the PWM period is 8.32 ns.
    If the HRDDIS bit is set, the smallest unit of measure
    for the PWM duty cycle, phase offset and dead time is
    8.32 ns.



     
    Regards,

    Dave

    Sometimes I just can't help myself...
    #5
    Mike017
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/04 14:32:37 (permalink)
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    Hi,
    The comments may not not be  up to date but the code is what I used for my earlier post.
        // The PWM clock period here is set up by setting the aux clock 
     PWMCON5bits.ITB = 0; // 0 = PTPER register provides timing for this PWM generator
     PWMCON6bits.ITB = 0; // 0 = PTPER register provides timing for this PWM generator
     PWMCON5bits.MDCS = 0; // 0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
     PWMCON6bits.MDCS = 0; // 0 = PDCx and SDCx registers provide duty cycle information for this PWM generator
      PTCONbits.PTEN = 0; // Disable the PWM Module
                PTPER = 48077; // PTPER = see FRM Section 43.6.1 or below
                    // PTPER = ((1 / 20kHz) / 1.04ns) = 2404, where 20kHz
            // is the desired switching frequency and 1.04ns is PWM resolution. */

     PTCON2bits.PCLKDIV = 0b000; // PWM clock divider ... 0b000 = div by 1

     IOCON5bits.PENH = 1; // PWMx is controlled by PWM module.... Forward - Left
     IOCON5bits.PENL = 0; // PWMx is controlled by GPIO module
     IOCON6bits.PENH = 1; // PWMx is controlled by PWM module .... Forward - Right
     IOCON6bits.PENL = 0; // PWMx is controlled by GPIO module

     IOCON5bits.POLH = 0; // Hi switches set to active high, 0 = high
     IOCON6bits.POLH = 0;
     IOCON5bits.PMOD = 0b00; // 0b00 = complementary mode - low sides not used
     IOCON6bits.PMOD = 0b00; //
     
          PDC5 = 20000; // Forward-Left...Primary Duty Cycle... Min = 0x0008
          PDC6 = 20000; // Forward-Right
      
        PTCONbits.PTEN = 1; // Enable the PWM Module

     
    I hope the formatting doesn't get too wrecked.
     
    Good Luck,
    Mike
    post edited by Mike017 - 2016/02/04 14:34:07
    #6
    Alec82
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/05 00:50:29 (permalink)
    0
    Now I understand the background, an 'accidentally' configured power saving mode tricked me. :)
    So, thank you Mike and Dave!
    #7
    torri
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/05 05:28:32 (permalink)
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    Mike017
    Hi,
    The comments may not not be  up to date but the code is what I used for my earlier post.
    [...]
                PTPER = 48077; // PTPER = see FRM Section 43.6.1 or below
                    // PTPER = ((1 / 20kHz) / 1.04ns) = 2404, where 20kHz
            // is the desired switching frequency and 1.04ns is PWM resolution. */
    [..]




    Hi
     
    But in Section 43.6.1 appears this (sorry about the size)

    So what's the correct expression for PTPER?
    #8
    davekw7x
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/02/05 09:47:57 (permalink)
    3 (1)
    torri

    Mike017
         // PTPER = ((1 / 20kHz) / 1.04ns) = 2404, where 20kHz


    That is correct, assuming that the PWM frequency is such that the PWM period is 1.04 ns.  That is, ACLK is equal to, nominally, 120 MHz, with the PWM Input Clock Prescaler divider set to 1


     
    Now:
     
     
    That is the expression for any value of ACLK, not just for ACLK = 120 MHz.  Note that this is a little more precise because the "- 8" apparently uses knowledge of some internal delays in the implementation for this family.
     
    Other than that, the two expressions are equivalent.
     
    Note that 1 / (120 MHz * 8) = 1.041666... nanoseconds, so that's the resolution in for 120 MHz ACLK, and that's where the 1.04 comes into the first equation.
     

    Regards,

    Dave
     

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    Sometimes I just can't help myself...
    #9
    dreke86
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/03/02 16:10:29 (permalink)
    3 (1)
    Are you using Center-Aligned mode or Edge-aligned mode?
    As per datasheet: For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions is 8.32 ns.
     
    [update: ignore this comment, I saw the other ones on the thread just now]
    post edited by dreke86 - 2016/03/02 16:12:16
    #10
    jnewcomb75
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/06/15 01:26:25 (permalink)
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    So... Is dsPIC33FJ64GS 1.04ns PWM resolution without jitter possible when driven from crystal??
     
    Is it possible to change the output waveform generated by the PWM by exactly 1.04ns increments? - or am I just flogging a dead horse??
     
    Try as I might, if I don’t mask the lower 3 LSBs of the PTPER (Period) and PDC (duty) registers I get ~ 8ns jitter on the waveform which is not good for my application. Is this by design? Is the extra accuracy obtained through dithering? The datasheet convinces me this should not be the case..
     
    If I mask the 3LSBs as a suggested fix, I then have less fine control of the PWM frequency, which I do need..
     
    I am clocking the PWM from Fvco fed from the 8MHz crystal and my code is as per the datasheet DS700000323G Page 39 Example 5-3
    I am using code based on the PWM example from the product page for the dsPIC33FJ64GS – but I’ve tried many other PWM configuration combinations / permutations.
     
    I’m not in any kind of power save mode in the AUXCONx register, not using centre aligned, dead time and phase and not important – I’m just using it as a clock and have set these to zero.
    My generated waveform of 60KHz ~50% duty is well away from the max / min duty and period values where 1.04ns accuracy is obtainable (according to the datasheet)
    I get the same problem if I use 'independent time base mode' PWMCONx:ITB(bit9) and specify the period in PHASE5 register
    I've tried endless combination and permutations and have not managed to find the winning formula.
    I'm beginning to doubt it can be done for period control and the 'dither' is by design.
     
    I found this posts but I’m still none the wiser.
     
     
    !!!!!!!!!!!!!!!!!!!!!!!!!!!
    EDIT.. I found it after writing this... Posted here so you don’t fall into the same trap...
    Datasheet DS700000323G p38 states in the notes:
    “The minimum PWM resolution when Fvco is the clock source for the Auxiliary Clock is 8.32 ns.”
    Also a note in DS70000591F-page193 about this.
     
    I’ve been looking at the PWM setup, but I should be studying the ACLK (auxiliary clock generator) DS70005131A-Page 4 Fig 1-2.
    The note above infers SELACLK must be set to ‘1’
    If that’s the case, the only route left for your crystal to drive the PWM is through POSCCLK. We get the following setup:

               /* In DS700005131A-Page4, fig 1-2, select POSCCLK to drive AUX CLK*/
                ACLKCONbits.ASRCSEL = 1;
                /* Dont select the 7.37MHz clock */
                ACLKCONbits.FRCSEL = 0; 
                /* Enable the Aux PLL */
                ACLKCONbits.ENAPLL = 1;
                /* Use POSCCLK (128MHz) as the PWM / ADC clock source*/
                ACLKCONbits.SELACLK = 1;
                /* Divide Auxiliary clock by 1 */
                ACLKCONbits.APSTSCLR = 7;

    Any hey presto accurate jitter free clocks (Only tested using complementary mode)
     
    BUT – and it’s a big butt.. I have an 8MHz crystal, the POSCCLK feeds directly from the XTL which is then routed to the APLL. DS70000591F-page 384 OS57 states max / min input to the APLL is 7Mhz – 7.5MHz.  The 8MHz works on my desk, but I would not risk on a product in the field given future silicon revisions / chip batches / temperature ranges / service life etc..
     
    I have tried feeding the APLL with the FRCCLK while selecting the Pvco to drive ACLK, but the jitter comes back. If you find a way to fudge it with 8MHz, please do post!
     
    So.. If you want 1.04ns resolution jitter free from the crystal I suggest you use a 7.3728MHz crystal. At least when you divide by 64 it starts working nicely with all the standard UART baud rate.
     
    And another thing you should be aware of..  Last 3 LSBs of the duty and period register are obtained using a repeating dithering pattern (filtered) to achieve 1.04ns resolution. I see noise creeping through the filter of 1ns of jitter on my 2.5G scope. This is in contrast to an unmeasurable amount of jitter when the last 3 LSBs are masked.
    The jitter does not accumulate so setting the scope with a delayed trigger of 100ms still shows about 1ns of jitter. It this is a problem for you they you are back to 8ns resolution. If you find otherwise or anything further to add, please post here.
     
    I also have a policy that every one of my posts must contain the word 'fudge'.
    Hope you don't waste a whole afternoon on this like I did!
    post edited by jnewcomb75 - 2016/06/16 09:41:26
    #11
    Stampede
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2016/06/21 01:13:38 (permalink)
    3 (1)
    Hi,
     
    jnewcomb75
    So... Is dsPIC33FJ64GS 1.04ns PWM resolution without jitter possible when driven from crystal??

    After reading that, I would have immediately said "use a 7.5MHz" crystal, which is what you found out yourself in the end.
    jnewcomb75
    And another thing you should be aware of..  Last 3 LSBs of the duty and period register are obtained using a repeating dithering pattern (filtered) to achieve 1.04ns resolution. I see noise creeping through the filter of 1ns of jitter on my 2.5G scope. This is in contrast to an unmeasurable amount of jitter when the last 3 LSBs are masked.

    I need to investigate that. It seems that the technology implemented by microchip is described in this patent:
    http://www.google.de/patents/US7508900
     
    Havent thought it completely through, but in seems indeed that there is a pulse pattern produced as a function of the 3 LSBs, if you are refering to fig.1
    #12
    Alec82
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2020/01/08 05:10:48 (permalink)
    4 (1)
    Hi All!

    After many years I tried to use the newer PIC32MK with PWM module, but without any confidence (as the new PIC32MK1024MCF100 is a big error itself). So I got back to dsPIC33FJ GS series, since the 32MK doesn't seem to be faster or better for my application and even the PWM module is worse (the whole chip is full of errors and PWM has lower resolution). As I read other's posts in this old thread started by me it looks like many people had problems with resolution and jittering with the older GS serie. And they thought that they made something wrong with the setup. But they didn't. There's no POSC 8 / 7.5 or FRC 7.37MHz issue, no accidentally setup for center aligned mode, nothing.
     
    I opened the errata of dsPIC33FJ64GS610 and point 36 says if you choose PCLKDIV 1:1 then you get jittering. All of us tried to make it work perfectly for years and we were suspecting ourselves to be dumb, but in 2019/09 point 36 was added to the errata which states you can't make jitter-free output with 3LSB resolution when you use 1 / 5 / 6 divisors. Workaround is to use different divisor. For example, divisor 2 is a solution, but with that you can't achieve the 1.04ns resolution. Because... AUX clock PLL output has to be 120MHz for proper operation (112..120). Postscaler has to be 1:1 because PWM clock has to be 120Mhz for proper operation, too. You can't raise it for its double and after divide it by 2 with PCLKDIV. So, PWM clock is fixed to 120Mhz and PCLKDIV cannot be 1:1 otherwise you have jitter. Next smallest divider is 1:2, so the achievable highest resolution is the half of the 1.04ns resolution, which is 2.08ns.
     
    Is it right? I think it is.
     
    So, after 3-4 years, for my first question.. the answer is a straight NO.
    The product is still advertised in the feature section "High speed PWM" with 1.04ns resolution. How can that be...
    #13
    T Yorky
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    Re: dsPIC33FJ64GS610 - have anyone ever achieved 1.04ns real resolution? 2020/01/09 04:48:37 (permalink)
    0
    There are a lot of issues with the HS PWM. I have used the 33FJ16GS502. Simple complementary mode has an errata issue this is the workaround...
    In order to avoid the <8 ns glitch to be propagated
    into the MOSFET gate driver, a low-pass filter
    (e.g., resistor-capacitor network) should be
    implemented between the dsPIC® DSC PWMx
    output pin and the gate driver IC input pin.
    ... I'm sure MChip would admit that this means that it is not good for 1.04nsec.
    #14
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