So... Is dsPIC33FJ64GS 1.04ns PWM resolution without jitter possible when driven from crystal??
Is it possible to change the output waveform generated by the PWM by exactly 1.04ns increments? - or am I just flogging a dead horse??
Try as I might, if I don’t mask the lower 3 LSBs of the PTPER (Period) and PDC (duty) registers I get ~ 8ns jitter on the waveform which is not good for my application. Is this by design? Is the extra accuracy obtained through dithering? The datasheet convinces me this should not be the case..
If I mask the 3LSBs as a suggested fix, I then have less fine control of the PWM frequency, which I do need..
I am clocking the PWM from Fvco fed from the 8MHz crystal and my code is as per the datasheet DS700000323G Page 39 Example 5-3
I am using code based on the PWM example from the product page for the dsPIC33FJ64GS – but I’ve tried many other PWM configuration combinations / permutations.
I’m not in any kind of power save mode in the AUXCONx register, not using centre aligned, dead time and phase and not important – I’m just using it as a clock and have set these to zero.
My generated waveform of 60KHz ~50% duty is well away from the max / min duty and period values where 1.04ns accuracy is obtainable (according to the datasheet)
I get the same problem if I use 'independent time base mode' PWMCONx:ITB(bit9) and specify the period in PHASE5 register
I've tried endless combination and permutations and have not managed to find the winning formula.
I'm beginning to doubt it can be done for period control and the 'dither' is by design.
I found this posts but I’m still none the wiser.
EDIT.. I found it after writing this... Posted here so you don’t fall into the same trap...
Datasheet DS700000323G p38 states in the notes:
“The minimum PWM resolution when Fvco is the clock source for the Auxiliary Clock is 8.32 ns.”
Also a note in DS70000591F-page193 about this.
I’ve been looking at the PWM setup, but I should be studying the ACLK (auxiliary clock generator) DS70005131A-Page 4 Fig 1-2.
The note above infers SELACLK must be set to ‘1’
If that’s the case, the only route left for your crystal to drive the PWM is through POSCCLK. We get the following setup:
/* In DS700005131A-Page4, fig 1-2, select POSCCLK to drive AUX CLK*/
ACLKCONbits.ASRCSEL = 1;
/* Dont select the 7.37MHz clock */
ACLKCONbits.FRCSEL = 0;
/* Enable the Aux PLL */
ACLKCONbits.ENAPLL = 1;
/* Use POSCCLK (128MHz) as the PWM / ADC clock source*/
ACLKCONbits.SELACLK = 1;
/* Divide Auxiliary clock by 1 */
ACLKCONbits.APSTSCLR = 7;
Any hey presto accurate jitter free clocks (Only tested using complementary mode)
BUT – and it’s a big butt.. I have an 8MHz crystal, the POSCCLK feeds directly from the XTL which is then routed to the APLL. DS70000591F-page 384 OS57 states max / min input to the APLL is 7Mhz – 7.5MHz. The 8MHz works on my desk, but I would not risk on a product in the field given future silicon revisions / chip batches / temperature ranges / service life etc..
I have tried feeding the APLL with the FRCCLK while selecting the Pvco to drive ACLK, but the jitter comes back. If you find a way to fudge it with 8MHz, please do post!
So.. If you want 1.04ns resolution jitter free from the crystal I suggest you use a 7.3728MHz crystal. At least when you divide by 64 it starts working nicely with all the standard UART baud rate.
And another thing you should be aware of.. Last 3 LSBs of the duty and period register are obtained using a repeating dithering pattern (filtered) to achieve 1.04ns resolution. I see noise creeping through the filter of 1ns of jitter on my 2.5G scope. This is in contrast to an unmeasurable amount of jitter when the last 3 LSBs are masked.
The jitter does not accumulate so setting the scope with a delayed trigger of 100ms still shows about 1ns of jitter. It this is a problem for you they you are back to 8ns resolution. If you find otherwise or anything further to add, please post here.
I also have a policy that every one of my posts must contain the word 'fudge'.
Hope you don't waste a whole afternoon on this like I did!
post edited by jnewcomb75 - 2016/06/16 09:41:26