The wrap up:
I have created a small program to test several 12F chips and a couple of 16F chips for Sleep current:
- Configs: internal osc=4MHz, wdt=off, mclr=off, bor=off, clkout=off (details depend on chip)
- Pulse an LED for 100K NOPs (100ms) to show program has run and to avoid using any timers.
- Change the ports to inputs and disable any weak pull ups if exist in chip. (external 10K pull downs used on each port pin).
- In some chip tests the ports were changed to outputs and set to 0V before sleep. The PGM port was fitted with a 10K pull down.
- Vregpm=1 (for 12F1840)
- Put the chip to Sleep
Test board without chip and 2x 100nF ceramic capacitors on Vdd <100nA @3V
16F690 <100nA on Demo PCB, ports outputs and set to 0V
16F887 <100nA ports outputs and set to 0V, RE3 with 10K pull down.
12F1840 approx 3.7uA @3V, ports output at 0V, RA3 10K pull down, Vregpm=1
12F1840 approx 36uA @3V, ports output at 0V, RA3 10K pull down, Vregpm=0
12LF1840 <100nA @3V, ports output at 0V, RA3 10K pull down.
In the last 3 tests, very similar code was used for the 12LF1840 and the 12F1840.
The 12F1840 included the extra Vregpm code.
I haven't solved why the 12F1840 draws more current than expected.
I am going to use the 12LF1840 for my project and get back to the main project code.
Attached is some code used in tests.
post edited by Gordy7 - 2013/03/06 00:52:40