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phy and magnetics ethernet pcb layout

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roundrocktom
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Re:phy and magnetics ethernet pcb layout 2012/11/19 13:58:56 (permalink)
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Freisen --
Place the Ethernet PHY as close to the PIC micro as possible.
Try to maintain 100 Ohm differential impedance on the TX and RX pair to your connector.  Ideal is an impedance matched connector to the daughter board.
 
Then the magnetic next to the RJ45 connector.
 
MRP -- It isn't that the manufactures "want to play it safe", but really wants your design to succeed.  The difference between a good design and a great design is passing all EMC testing!  SMSC recommendations are based on years of customer feedback, ideal is when everything passes first time!
 
Even if FCC testing is not required for your design, the Ethernet cable should be able to run 100 meters.   I have customers running at 130 meter cable lengths (gas pump), which isn't guaranteed -- but possible using excellent cat5e cable.
 
SMSC Guidelines are well hidden, but an excellent resource:
Start here:
https://www2.smsc.com/mkt/web_lancheck.nsf
 
Notice there are five sections:
Schematic
Magnetic
Layout
Routing
Additional Information.
 
Click on the section, and follow it to the part your working on and it has some great information.
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friesen
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Re:phy and magnetics ethernet pcb layout 2012/11/19 14:12:14 (permalink)
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I can't get a straight answer from lantronix about latency, reconsidering here.  A couple questions.
 
How will performance compare between a pic32mx460f512l + enc624J600 and 795 + PHY?
 
Will I have more time to manage processing with the first scenario?  I would like < 2 ms queue to packet times, and packet to serial/spi times.

Erik Friesen
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roundrocktom
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Re:phy and magnetics ethernet pcb layout 2012/11/19 19:06:24 (permalink)
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>  How will performance compare between a pic32mx460f512l + enc624J600 and 795 + PHY?

If you are running the enc624J600 in 16 bit mode,  I would think performance would be similar to the 795+PHY.   795 has additional DMA channels, which would give it the nod for performance.  The only way to get a realistic performance numbers is to test both side by side.
 
> Will I have more time to manage processing with the first scenario?  I would like < 2 ms queue to packet times, and packet to serial/spi times.
 
I need to look closer at the 795 to see what size packets it can send.
 
Other thoughts is how "green" does this device need to be? Do you want to put it into a deep sleep and have "Wake on LAN" (when a specific
packet is sent, it wakes up the processor via an interrupt)?  Do you need EEE (Energy Efficient Ethernet)? If yes, then 795 + LAN8740 would be my choice.
 
 
 
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friesen
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Re:phy and magnetics ethernet pcb layout 2012/11/19 19:29:15 (permalink)
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Actually the performance numbers from MC tcp/ip help are a bit surprising.  The gain from pmp isn't that much.  795+phy is almost twice as fast as the next lowest, with udp 4x as fast. 

Erik Friesen
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Re:phy and magnetics ethernet pcb layout 2012/11/19 19:39:49 (permalink)
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I am still trying to estimate latency though.  Most of the packet payloads will be less than 10 bytes, with occasional 100 or so byte packets.
 
Its for interfacing to a Symetrix radius dsp. 

Erik Friesen
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roundrocktom
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Re:phy and magnetics ethernet pcb layout 2012/11/20 12:27:34 (permalink)
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Since the communication is point to point (no collisions),  you should be able to calculate how long it takes to create a packet, and send it out from the PIC.   On the Radius DSP, do the same from incoming packet.    Nothing else running, this will give you the best case for lowest latency.  The minute you start running other code, RTOS, etc... you know latency will only get longer, so you still need to measure worst case on the systems running.

I'd look at setting a GPIO high at the beginning of the Ethernet routine,  then low once finished.   Do the same on the DSP.   In the midst of the data
send one unique packet (comparing the data on the dsp side).  At least you can see if this is possible.
 
IEEE1588 v2 does allow time stamping, but with point to point and the use of a GPIO between processors to signal when data is ready, at least you know when the data was collected.
 
 
 
 
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friesen
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Re:phy and magnetics ethernet pcb layout 2012/11/20 17:44:35 (permalink)
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Has anyone implemented something similar on a two layer pcb, or is it unworkable to try?

Erik Friesen
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maxruben
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Re:phy and magnetics ethernet pcb layout 2012/11/21 01:14:32 (permalink)
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Not on two separate boards but here is a two layer home-caded/etched/drilled/mounted board with a PIC32MX695F512H, a LAN8720 phy (RMII interface) and a magjack rj45 connector.
 
This is for a home project so I havn't made any EMC testings on it. But it works fine. It is currently used to control mains connected lamps on and off through a web page, a radio transmitter (the MRF24J40 on the board) and a hacked mains remote control. This way I can control some of my lamps  from my smartphone.
 




/Ruben
 
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friesen
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Re:phy and magnetics ethernet pcb layout 2012/11/21 04:35:45 (permalink)
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There won't be any emc consideration on this project, other than that I want it to be in reasonable limits.  No testing.
 
The starter kit has the phy less than .5" from the magnetics, so I guess they ignored the 1" rule.

Erik Friesen
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roundrocktom
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Re:phy and magnetics ethernet pcb layout 2012/11/21 07:11:58 (permalink)
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It's practically impossible to get a two layer board to pass radiated emissions and ESD testing.   If those test are not a concern, then all you have to worry about is signal integrity issues, just maintain the 100 ohm differential trace and you'll be fine.
 
On that 1" distance, it does help pass EMC testing.   Also, when space allow, using a separate magnetic and RJ45 jack really helps.  Obvious some designs have such a tight sizing that is not possible, but if you have the space and want to pass FCC the first time, it really helps.
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Muenchow
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Re:phy and magnetics ethernet pcb layout 2012/11/22 09:00:32 (permalink)
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Although MX795 is promising better performance by the DMA MAC interface, I expect that most latency will be generated in TCP/IP stack software packet processing and thus mainly depend on processor clock speed and additional performance settings.
 
Regarding the suggested >25 mm PHY to magnetics distance suggested in the SMSC application note, I must admit that I don't know how it might be validated. The document is talking about intended isolation, but which coupling mechanisms are considered here? I believe that various assumptions can be brought up in empirical EMC design, but they are not necessarily well-founded and the results not necessarily reproducable. The suggestion may refer to ground plane coupling.
   
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roundrocktom
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Re:phy and magnetics ethernet pcb layout 2012/11/26 10:59:17 (permalink)
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The spacing has been validated over testing 100’s of designs.  I do not have a model of the capacitive and inductive coupling, but empirical testing has shown the 1” spacing does help reduce the harmonics.  The RX and TX traces are sandwiched between a ground plane and VDD1A/VDD2A Plane, and kept at 100 Ohms differential impedance.  The 1” to 3” recommended distance between the transformer and IC does add a little capacitance between these lines and ground, which helps reduce high frequency noise.     Having the option of adding a 10-15pfd cap between those four (TX and RX) lines to ground is also a good option.
 
In some cases the board doesn’t have the space available and the RJ45 connector (magnetic jack) are very close to the PHY.  Do try to follow the layer recommendation, and have the cap option available.  These boards will pass, but occasional needs to have the board re-spun out to pass the tighter FCC class B testing. 
 
The goal is to have boards pass on first time testing.  Separate Rj45, magnetics, and IC spacing helps quite a bit.  If space constrained, and/or using a magnetic jack,  it may take a little more effort in passing EMI testing (those 10 pfd caps should only be populated after first pass testing, as too much capacitance may cause other issues). 
 
The 1” spacing rule is pretty much an industry standard. There is also a rule to keep any other high-speed signaling (crystals, the Phy itself) 1” away from the board’s edge as well.
 
 
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Muenchow
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Re:phy and magnetics ethernet pcb layout 2012/11/28 15:07:23 (permalink)
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roundrocktom
The spacing has been validated over testing 100’s of designs.  I do not have a model of the capacitive and inductive coupling, but empirical testing has shown the 1” spacing does help reduce the harmonics.  The RX and TX traces are sandwiched between a ground plane and VDD1A/VDD2A Plane, and kept at 100 Ohms differential impedance.  The 1” to 3” recommended distance between the transformer and IC does add a little capacitance between these lines and ground, which helps reduce high frequency noise.  Having the option of adding a 10-15pfd cap between those four (TX and RX) lines to ground is also a good option.

I have no problems to accept this as an empirical validated EMC measure. With the additional explanations and reference to additional capacitors, it makes sense. It suggests that the PHYs show common mode leakage at harmonic frequencies that are not sufficiently attenuated by usual ethernet magnetics. If it's true, good RF common mode chokes like Wuerth CNSW could supress it effectively.
 
The board edge distance point sounds very reasonable, too. 
Regards,
Frank
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