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Hot!diferences between . . .

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daraga
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2011/02/02 02:35:15 (permalink)
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diferences between . . .

Hi Hi to all
 
Could anyone explain me the diferences between
 
     incf        FSR0,f
 
 
    incf        FSR0L,f
    btfsc      STATUS,Z
    incf        FSR0H,f
 
 
 When can I use the first or the second example? Which are the diferences?
 
Thanks
daraga
 
 
#1

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    ppater
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    Re:diferences between . . . 2011/02/02 02:52:47 (permalink)
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    The first form is meaningless.
    FSR0 is not a register, it is only a constant that is used to indicate that the target is FSR0 in some instructions like LFSR.


    Best regards,
    Philippe.

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    #2
    Stefan Uhlemayr
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    Re:diferences between . . . 2011/02/02 04:42:36 (permalink)
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    daraga

    ... Could anyone explain me the diferences between
     
         incf        FSR0,f
     
     
        incf        FSR0L,f
        btfsc      STATUS,Z
        incf        FSR0H,f
     
     
     When can I use the first or the second example? Which are the diferences? ...
    As Philippe pointed out already, the first one can't work. If you want to learn about indirect addressing in the PIC18-architecture and/or want to increase the a FSRx-pointer with one instruction, then have a look to the chapter 7.7.6.1 in the PIC18-complete-reference-manual ("POSTINCn"):
    ORIGINAL: Flying with HardWare Favorites Gallery List

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    PICmicro 18C MCU Family Reference Manual: from Microchip

    Hope this helps, Smile
    Stefan
    #3
    DarioG
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    Re:diferences between . . . 2011/02/02 09:21:55 (permalink)
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    It happened to me to use a similar thing... today, while "optimizing" my BAM (SW_PWM) code. And, in C18, you can use either forms: the FSR0x are 8 bit parts treated as such, while FSR0 is a 16 bit variable.

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    #4
    jtemples
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    Re:diferences between . . . 2011/02/02 11:12:06 (permalink)
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    ppater

    FSR0 is not a register, it is only a constant

    FSR0L and FSR0H are real registers that you can read and write just like any other register.


    #5
    ppater
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    Re:diferences between . . . 2011/02/02 15:23:45 (permalink)
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    jtemples

    ppater

    FSR0 is not a register, it is only a constant

    FSR0L and FSR0H are real registers that you can read and write just like any other register.


    What's the purpose of this? What it is supposed to clarify better than previous posts?

    Best regards,
    Philippe.

    Pic Micro Pascal for All!
    #6
    BitWise
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    Re:diferences between . . . 2011/02/03 03:10:52 (permalink)
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    On high-performance (18F) devices their are three indirect file pointer registers. Each pointer occupies two memory locations, one for the low byte FSRxL and one for the high byte FSRxH (where the 'x' is 0, 1 or 2). Only the four least significant bits of the high byte are used to make a 12-bit file register address.

    The devices have a double word instruction 'LFSR' that allows the high and low parts of a FSR register to be loaded with a constant value. The syntax for the instruction is:

    LFSR f,k

    where f is 0,1 or 2 and k evaluates to a constant in the range 0 to 4095.

    The device include files define the symbols FSR0, FSR1 and FSR2 for use in this instruction. As these constants evaluate to 0, 1 and 2.T hey do not correspond to the actual register locations.

    After loading a value into an FSR you would normally change its value using the PREINCx, POSTINCx, POSTDECx psuedo registers that access memory and change the FSR value (doing a 12-bit increment or decrement) at the same time. For example

    LFSR FSR0,BUFFER     ; Point FSR0 at a buffer area
    MOVF POSTINC0,W    ; Fetch a single byte while advancing the pointer


    post edited by BitWise - 2011/02/03 03:13:44

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    #7
    erco
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    Re:diferences between . . . 2020/04/13 15:42:40 (permalink)
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    Old thread I know, but I too found myself asking the OP's question as I was trying to make sense of an example from the MPASM user guide (xc8/v2.10/mpasmx/docs/MPASM_MPLINK_User_Guide.pdf, sec. 7.6.1) showing what appears to be a generalized macro to unpack 32 bits into 4 consecutive bytes, using "INCF FSR,F" to advance the FSR.

    The macro example is for a 16F, whereas I'm using an 18F, where there is no single FSR, but three (FSR0 thru FSR2), so it seemed by extension that "INCF FSR0,F" would be the appropriate thing. It compiled OK, but stepping through the debugger showed FSR0 didn't change, and that was making me crazy for probably longer than it should have.

    When you're new to this stuff, you don't know what's wrong; I thought it might be a problem with the bank select, or those little ",x" suffixes, or some other newbie mistake before realizing "nope, this isn't working at all". So I took to the data sheet where I found different examples using LFSR and POSTINC0 (as shown above) to auto-advance the FSR0 register in 12bit fashion, and was finally getting predictable results.


    Also found this thread, which helped to understand that while manipulating "FSR0" won't work, manipulating the separate byte registers  "FSR0L" and "FSR0H" would work, so e.g. "INCF FSR0L" does in fact work (to advance in 8bit fashion, wrapping past 0xff)

    I guess I'm surprised the compiler doesn't warn about the use of "INCF FSR0" for the 18x processors, as that would have certainly helped me. It seems like a pitfall easy to make.
    post edited by erco - 2020/04/13 16:13:53
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    1and0
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    Re:diferences between . . . 2020/04/13 16:19:01 (permalink)
    5 (1)
    erco
    I guess I'm surprised the compiler doesn't warn about the use of "INCF FSR0" for the 18x processors, as that would have certainly helped me. It seems like a pitfall easy to make.

    That is because in your device specific include file, they are defined as:
    FSR0 EQU 0
    FSR1 EQU 1
    FSR2 EQU 2

     
    PIC18 devices do not have registers with these names nor plain FSR. The PIC18 datasheets document these registers as FSR0L, FSR0H, FSR1L, FSR1H, FSR2L, and FSR2H. ;)
     
    post edited by 1and0 - 2020/04/13 16:23:15
    #9
    erco
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    Re:diferences between . . . 2020/04/13 16:44:53 (permalink)
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    I was just imagining the assembler could make a preliminary pass at the source to check for the use of FSR0/1/2 in the context of e.g. INCF/DECF, before the expansion of the equates into values, just a service to the user to warn against typos or mistaken newbie assumption.
    #10
    ric
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    Re:diferences between . . . 2020/04/13 16:50:56 (permalink)
    5 (1)
    The assembler is not smart enough to do that. These are all just labels from its point of view.
    There really is very little hand holding when you are working in assembler, you need to move up to C to get a bit more syntax checking.
     

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    dan1138
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    Re:diferences between . . . 2020/04/13 17:00:20 (permalink)
    5 (2)
    The Microchip PICALC, MPASM and MPASMWIN assemblers along with the Hi-TECH ASPIC assembler are deep dark pits just waiting for an unwary developer to fall in and be covered by bugs.
     
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    Mark Yampolsky
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    Re:diferences between . . . 2020/04/14 00:03:42 (permalink)
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    erco
    Also found this thread, which helped to understand that while manipulating "FSR0" won't work, manipulating the separate byte registers  "FSR0L" and "FSR0H" would work, so e.g. "INCF FSR0L" does in fact work (to advance in 8bit fashion, wrapping past 0xff)

    I guess I'm surprised the compiler doesn't warn about the use of "INCF FSR0" for the 18x processors, as that would have certainly helped me. It seems like a pitfall easy to make.



    In addition to the Assembler Guide, you should study and datasheet of the MCU in terms of its core architecture and command system. Then there will be no strange requirements for the assembler preprocessor...
    #13
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