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12LF1822 bsf seems to have a bug

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nshimada
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2010/10/09 21:49:07 (permalink)
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12LF1822 bsf seems to have a bug

Bsf instruction of 12LF1822 seems to have a bug.

TEST1 of list 1 output waveform like Graph 1 by MPLAB SIM & Simulator Logic Analyzer, but real 12LF1822 output Graph 2.
TEST2 output Graph 1 with real 12LF1822.

I think, by followed the same registered bsf, this unexpected behavior seems to appear.
Changing the instruction order or inserting nop like the TEST2 make code work correctly.


Graph 1

          +----------------------------------------------
RA0       |
    ------+
                  +--------------------------------------
RA1               |
    --------------+
                          +------------------------------
RA2                       |
    ----------------------+

RA3
    -----------------------------------------------------
                                          +--------------
RA4                                       |
    --------------------------------------+
                                                  +------
RA5                                               |
    ----------------------------------------------+



Graph 2

          +-------+       +-------+       +-------+
RA0       |       |       |       |       |       |
    ------+       +-------+       +-------+       +------
                  +-------+       +-------+       +------
RA1               |       |       |       |       |
    --------------+       +-------+       +-------+
                          +-------+       +-------+
RA2                       |       |       |       |
    ----------------------+       +-------+       +------

RA3
    -----------------------------------------------------
                                          +-------+
RA4                                       |       |
    --------------------------------------+       +------
                                                  +------
RA5                                               |
    ----------------------------------------------+



List 1

    movlb   1       ; bank 1
    clrf    TRISA   ; all output
    movlb   0       ; bank 0


TEST1:
    clrf    PORTA
    nop

    bsf     PORTA,0
    bsf     PORTA,1
    bsf     PORTA,2
    bsf     PORTA,3
    bsf     PORTA,4
    bsf     PORTA,5

TEST2:
    clrf    PORTA
    nop

    bsf     PORTA,0
    nop
    bsf     PORTA,1
    nop
    bsf     PORTA,2
    nop
    bsf     PORTA,3
    nop
    bsf     PORTA,4
    nop
    bsf     PORTA,5
    nop



post edited by nshimada - 2010/10/09 22:04:40
#1

5 Replies Related Threads

    ppater
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    Re:12LF1822 bsf seems to have a bug 2010/10/10 01:04:33 (permalink)
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    This is not a bug but a nice feature from MCHP that makes a lot of messages in this forum...
    You are just experimenting the classic and famous RMW problem.

    Best regards,
    Philippe.

    Pic Micro Pascal for All!
    #2
    jtemples
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    Re:12LF1822 bsf seems to have a bug 2010/10/10 01:16:47 (permalink)
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    The PORT registers are for reading, not writing.  Write to the LAT registers.
    #3
    ppater
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    Re:12LF1822 bsf seems to have a bug 2010/10/10 02:01:15 (permalink)
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    jtemples
    The PORT registers are for reading, not writing.  Write to the LAT registers.

    Yes, but what a nice RMW problem! People like us can't pass this kind of beauty!
    I really don't understand the timing: the regularity is astounding! It mimics some kind of crazy counter...
    Is that a new undocumented stealth feature? (non iso-synchronous foolish counting)

    Definitely it goes in my archives!

    Best regards,
    Philippe.

    Pic Micro Pascal for All!
    #4
    Ian.M
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    Re:12LF1822 bsf seems to have a bug 2010/10/10 03:12:00 (permalink)
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    @nshimida; 
    Please could you re-test with 50pF capacitors to Vss on each Port A output pin  (anything from 33pF to 68 pF would do) before changing your elegant example program.  I think you will find that the test2 with the NOPs in between will also fail with a moderate capacitive load.  If you can take some oscilloscope screen shots and attach them ,it would be helpful in future when we are trying to convince others that it is worth coding defensively to avoid the RMW problem.

    There are two possible ways of fixing this:  Use LATx registers for all port writes (applicable to all enhanced midrange, PIC18 or better devices) or only do bit operations on a buffer in RAM then copy the whole byte to the port at once each time (the only solution for the standard midrange and baseline cores which do not have LATx registers).

    Here is a test 4 buffering the value to be output in W.  I leave it to you to add Test 3 using LATA.

    TEST4:
        movlw   0
        movwf   PORTA
        iorlw   1<<0 ;set bit 0
        movwf   PORTA
        iorlw   1<<1 ;set bit 1
        movwf   PORTA
        iorlw   1<<2 ;set bit 2
        movwf   PORTA
        iorlw   1<<3 ;set bit 3
        movwf   PORTA
        iorlw   1<<4 ;set bit 4
        movwf   PORTA
        iorlw   1<<5 ;set bit 5
        movwf   PORTA

    It would be more usual to construct the value to be written to the port in a file register (RAM) rather than in W, using normal BSF and BCF operations then copying it to the port via W, but I wanted to preserve the same timing as Test 2 so had to work in W.

    Do let us know how you get on.  There is a gallery of hints and tips that covers this issue (and many others) that I would like to see this topic linked to as a thoroughly tested and documented classic example of the problem.

    #5
    nshimada
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    Re:12LF1822 bsf seems to have a bug 2010/10/14 06:31:27 (permalink)
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    Thanks for reply. 

    I studied About RMW. 
    Maybe I could understand well. 

    I only have software osciloscope that use pc's sound input as it's probe. thus it couldn't capture the waveform. sorry. 
    Appropriate capacitor is not in my parts box. I'll try after I've got it. 

    Writing to LATA was work fine. TEST4 well too. 
    The essence of the problem is seems to unstability of pin output, I tried slow down the Fosc from 32MHz to 500kHz. This was output correct waveform too. 

    My source code use bit copy like BEFORE in following code many times. 
    Simply replacing to LATA is make the code to AFTER. This need large memory, CPU time and many of not important label. I tried to write to LATA via INDFx registor like AFTER2. This seems to work good. 
    Byte writing was not appropriate to my code that I making now. 



    BEFORE: 
        bsf     PORTA,0 
        btfss   PORTA,1 
        bcf     PORTA,0 

    AFTER: 
        movlb   1 
        bsf     LATA,0 
        movlb   0 
        btfsc   PORTA,1 
        goto    ENDAFTER 
        movlb   1 
        bcf     LATA,0 
        movlb   0 
    ENDAFTER: 

    AFTER2: 
        movlw   low(LATA) 
        movwf   FSR0L 
        movlw   high(LATA) 
        movwf   FSR0H 

        bsf     INDF0,0 
        btfss   PORTA,1 
        bcf     INDF0,0 



    #6
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