Lockedmain difference DMIPS and MIPS

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montanari9
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2008/04/03 07:46:35 (permalink)
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main difference DMIPS and MIPS

Hi, I was thinking...what is the difference between DMIPS and MIPS, I know that DMIPS is drhystone MIPS, which menas that this kind of measurement is refferent to some sort of padron test...but 1.0 DMIPS is equal to how much MIPS?

It's a silly question...but i was curious about this.

Thanks in advance
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    leon_heller
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    RE: main difference DMIPS and MIPS 2008/04/03 09:53:40 (permalink)
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    You can't compare them, AFAIK. MIPS simply refers to instruction execution rate for any program, and Dhrystone MIPS are calculated using a specific program.
     
    Leon
     

    Leon Heller
    G1HSM

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    montanari9
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    RE: main difference DMIPS and MIPS 2008/04/03 10:29:46 (permalink)
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    I see...but the 32 bits would have how many MIPS?

    Do you know?
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    leon_heller
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    RE: main difference DMIPS and MIPS 2008/04/03 11:54:38 (permalink)
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    It depends on the clock speed and the instruction set. You should be able to calculate it from the data sheet.
     
    Leon
     

    Leon Heller
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    montanari9
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    RE: main difference DMIPS and MIPS 2008/04/03 13:21:09 (permalink)
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    I see...i remember reading something about 80 Mhz...i'll start from this point and read it again

    tks

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    PIC32explorer
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    RE: main difference DMIPS and MIPS 2008/04/03 15:42:52 (permalink)
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    I think you can find a decent introduction at: http://en.wikipedia.org/wiki/DMIPS

    Hope this helps

    Lucio




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    westfw
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    RE: main difference DMIPS and MIPS 2008/04/17 18:34:43 (permalink)
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    There are essentially two aspects of CPU performance:
    1) How many instructions can the CPU execute in a second.
    2) How much actual WORK can the CPU do in one second.

    The first is controlled by CPU architecture, memory speed, and so on.  The second has those as variables, and add "how effective is the instruction set at doing the sort of work I want to do."  For instance, a PIC16xxx running at 20MHz executes 5 million instructions per second, but those instructions operate on 8bit data, and don't include things like multiply and divide.  But the instructions DO include a bunch of bit manipulation and IO instructions.  So if you compare the pic to, oh, the 5MHz 8088 in the original IBM PC (should be safe an inoffensive), the PIC will be faster than the 8088 at some things (in particular those things having to do with touching external hardware), and the 8088 will be faster at other things (16bit math.)
    For a long time, people tended to measure CPU performance with floating point benchmarks (fortran geeks they were, every one!)  There was a set of benchmarks developed  (1972!) called the Whetstone benchmarks that would measure a computers floating point performance.  Eventually, people started using computers for things other than math, and realized they needed a similar benchmark for non-floating-point (integer) performance.  This led to the Dhrystone benchmarks (get it?)

    So the PIC32 runs at 80MHz, and generally executes instructions in about 1 cycle, so it does close to 80MIPs. It also runs the Dhrystone benchmark at about 1.5DMIPS/MHz (also 1.5DMIPs/MIP), which shows a pretty efficient architecture (at the sort of application the Dhrystone measures.)  It's more than a tiny core run at very high speed.

    (This is one of the reasons you may have read the messages asking about pin-toggle speed.  It's pretty common for fast CPUs to incur a lot of overhead when they have to talk to the outside world; some of the ARM7TDMI toggle rates are pretty embarassing, and a 3GHz x86 cpu can't do IO instructions much faster than the ancient 8088 (not to mention the terrible things such instructions do to the pipeline/etc.))

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    zardoz1
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    RE: main difference DMIPS and MIPS 2008/04/17 22:32:26 (permalink)
    5 (1)
    It depends on the clock speed and the instruction set. You should be able to calculate it from the data sheet.

     
    Theoretically true, practically almost impossible. PIC32 performance influenced by a lot of things.
     
    1: Core runs 80MHz, Flash runs 20MHz, so in principle for every instruction there are three wait states
    2: The low flash speed is compensated for by the cache and the prefetch cache but cache misses introduce wait states and prefetching only works on linear code
    3: Data memory can be configured with a wait state
    4: Code can contain stalls when a register is filled and used in the next instruction as an address register
    5: Branch instruction have a branch delay slot which might not be filled and thus contains a nop
     
    Bottom line, you will never reach 80MIPS. 4 and 5 are for a large part taken care of by the compiler and the assembler which will reorder instructions such that these wait cycles occur less frequent.
     
    This topic has been dealt with many times before, read for instance here
     
    http://forum.microchip.com/tm.aspx?m=322135&mpage=1&#325463
     
    My conclusion is that performance can only be measured on your actual application and not by a static analysis of the code.


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