• AVR Freaks

What is the meaning of Shadowing a register?

Author
asimmittal
Starting Member
  • Total Posts : 44
  • Reward points : 0
  • Joined: 2007/11/29 23:12:32
  • Location: 0
  • Status: offline
2007/12/05 00:42:19 (permalink)
0

What is the meaning of Shadowing a register?

I was reading the attribute "shadow"


The shadow attribute causes the compiler to use the shadow registers rather than the
software stack for saving registers


I googled "shadow register files" and found a paper on "shadow register file architechture". This spoke about context switching, and scheduling etc.

In plain english, are shadow registers like a cache? but then assume that the controller is doing something, just then, and interrupt occurs, and it saves all its content on the stack... goes to the ISR, finishes it, comes back where it had stopped and pops the stack.

Now with shadow registers,assuming its like a cache... when the interrupt occurs, wont it again store contents onto this so called cache, execute the ISR, return and then bring contents back from the cache. How is it faster??

I read somewhere that shadow attribute is used in liason with the interrupt attribute and this causes a "fast ISR" or something like that?

What really happens?

Thanks
#1

5 Replies Related Threads

    DarioG
    Allmächtig.
    • Total Posts : 54081
    • Reward points : 0
    • Joined: 2006/02/25 08:58:22
    • Location: Oesterreich
    • Status: offline
    RE: What is the meaning of Shadowing a register? 2007/12/05 02:58:40 (permalink)
    0
    Well, I'd say that they're a kind af "the same register, with a double content". Something that can be used in its first "face" or in its second one.

    Don't know if you used to know Z80, which had some HL and HL' registers, again to be used in Interrupt context saving (specifically NMI, if I'm not wrong).

    A "shadow register" is inherently faster to access: no RAM cycles involved, and also no pointers/FIFO involved: in fact, you usually have only "one" shadow and not more than one.

    (in the end, something similar is done when creating a "shadow register" for a PORTx register)

    GENOVA :D :D ! GODO
    #2
    Olin Lathrop
    Super Member
    • Total Posts : 7463
    • Reward points : 0
    • Joined: 2004/02/26 17:59:01
    • Location: Littleton Massachusetts
    • Status: offline
    RE: What is the meaning of Shadowing a register? 2007/12/05 06:17:09 (permalink)
    0
    I googled "shadow register files" ...

    Don't google, read the manual.  In the dsPIC context, shadow register refer to where certain key registers can be saved.  This can be useful to decrease latency and overall cycles in the highest priority interrupt routine by using the PUSH.S and POP.S instructions.
    #3
    zardoz1
    Super Member
    • Total Posts : 1852
    • Reward points : 0
    • Joined: 2005/07/09 08:03:28
    • Location: 's-Hertogenbosch, The Netherlands
    • Status: offline
    RE: What is the meaning of Shadowing a register? 2007/12/05 08:48:30 (permalink)
    0
    can be useful to decrease latency and overall cycles in the highest priority interrupt routine

     
    Of course it would be obvious to use in the highest priority interrupt level but shadow registers are not restricted to be used with the highest priority ISR. They can be used at any interrupt level if the shortest latency is an absolute must. It is important when using them to use them only in interrupt routines at the same priority since there is only one set.
     
    This mechanism is a poor implementation of what it should be. The only registers saved are w0-w3 and I believe SR. In the PIC32 it is implemented the way it should be by shadowing all registers and not just a subset.


    AVIX
    the PIC32 & dsPIC/PIC24 RTOS with:
    - Zero Latency Interrupts
    - The best performance!
    - Integrated Power Management
    Download here: http://www.avix-rt.com/
    #4
    DarioG
    Allmächtig.
    • Total Posts : 54081
    • Reward points : 0
    • Joined: 2006/02/25 08:58:22
    • Location: Oesterreich
    • Status: offline
    RE: What is the meaning of Shadowing a register? 2007/12/05 08:51:42 (permalink)
    0
    OP posted his question in this forum, but I actually believed that a "broader" answer was desired... Smile
    (something like involving Z80 or PIC18 as well)

    GENOVA :D :D ! GODO
    #5
    Olin Lathrop
    Super Member
    • Total Posts : 7463
    • Reward points : 0
    • Joined: 2004/02/26 17:59:01
    • Location: Littleton Massachusetts
    • Status: offline
    RE: What is the meaning of Shadowing a register? 2007/12/05 10:06:47 (permalink)
    0
    They can be used at any interrupt level if the shortest latency is an absolute must.

    True.  In fact you can generalize this even further since they can be used in any code.  The only restriction is that there is one set, so some mechanism has to guarantee that there is never a attempt to use them more than one level deep.  You could, for example, decide to reserve them for use in a critical piece of foreground code where average cycles/loop is the important criterion, and occasional added latency caused by interrupts isn't a problem.
     
    That said, I have so far only used them for the highest priority interrupt routine, and that's most likely to continue.  It doesn't make much sense to worry about the few extra cycles of latency in lower priority interrupt routines when a higher priority interrupt can come a long and add a lot of extra latency.
     
    This mechanism is a poor implementation of what it should be. The only registers saved are w0-w3 and I believe SR.

    That's still useful in a lot of cases.  This sounds like a cost tradeoff.  At some point it doesn't make sense to burden the cost of all dsPICs with extra hardware that only a few will use.  I think they got the tradeoff about right, since most interrupt routines that are going to trash more registers are going to take more cyles and the extra benefit of the shadow registers becomes smaller proportionately.
    #6
    Jump to:
    © 2019 APG vNext Commercial Version 4.5