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henkebenke
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2021/03/08 16:48:06 (permalink)
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About cache areas vs non cached areas

Hi, when it comes to PIC programming, I have developed some "black holes" in my abilities.  The SPI is one subject - I always run into virtual swamps of ambiguities when dealing with those.
Another area is flash programming. The main reason for headache is the fact that the caching system behaves unexpected when the flash mem has been programmed.  So, I found out that the non cached areas are some sort of "safe havens".
But.....
Now I discovered yet another strangelet. After I burned the data into flash, I validated it with a home brewed version of memcmp().  I converted the addresses by using the KVA0_TO_KVA1() macro. But the validation failed. 
What I found was that converting the ram area from 0x80000000 to 0xa0000000 via said macro, gave a non valid result. Reading the ram at 0x800008a0 ( in this case ) gave the expected result, but reading 0xA00008a0 gave another value.
 
 What can we say about this? I read somewhere that the ram area is divided in a upper and lower half - has that something to do with it? 
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    NKurzman
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    Re: About cache areas vs non cached areas 2021/03/08 21:21:00 (permalink)
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    If you are flashing memory then you need to use the non-cachable memory address. When you read cached memory you may not be reading the memory itself you may be reading what is in the cache. What you get depends on what the CPU has cache and that is based on the code it is executing. Additionally certain profiles require the non-cached address. And as you probably know the flash memory requires the physical address.
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    Stefiff
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    Re: About cache areas vs non cached areas 2021/03/09 14:56:41 (permalink)
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    There is one simple rule. All hardware modules use only physical addresses, ie. without caching. Caching is used only for the software, your program. If a module needs to transfer information, it is always without caching. Variables in RAM must be without caching.
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    andersm
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    Re: About cache areas vs non cached areas 2021/03/09 16:57:26 (permalink)
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    StefiffThere is one simple rule. All hardware modules use only physical addresses, ie. without caching.

    You are conflating caching with mapping. It is true that peripheral memory accesses will not go through the caches, but neither will the CPU when using the KSEG1 region.
    #4
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