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Hot!PIC32MZ ADC DMA OC unsteady sample amount

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boiler
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2021/02/25 09:49:45 (permalink)
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PIC32MZ ADC DMA OC unsteady sample amount

Hi all,
basically my application to capture analog signals is working but I've issue with the amount of sampled data. My setup is that
Timer 3 -> triggers OC3 (for clock) -> triggers ADC -> triggers DMA -> triggers DMA interrupt after 1024 bytes. In DMA interrupt I trigger OC6 for a reset pulse and everything continues.
The issue is now that sometimes the pulse reset which should be triggered in DMA interrupt after 1024 bytes jitters. Sometimes I got 1022 bytes, sometimes 1028 bytes or clocks.
I'm not sure where to start to solve this issue. I've tried different timer oc/setups....clock rate is 500kHz up to 1MHz.
Any idea is appreciated.
Thanks a lot!
Best Mario
#1

7 Replies Related Threads

    boiler
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/02/26 07:17:00 (permalink)
    0
    I've done some more tests. I've replaced the ADC with a simple buffer to buffer copy, I can still see a jitter. Something like:
     
    1024
    1024
    1024
    1020
    1028
    1024
    1024
    1026
    1022
    1024
    1024
     
    The copied data is valid, the table above is from view of output pins clock and pulse reset. Using Timer 3 to trigger DMA copy byte per byte, then on "block transfer end" I do the pulse reset in ISR. This should be stable or?
    #2
    boiler
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/02/26 08:15:53 (permalink)
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    The jitter is not the biggest problem for me, but it looks like the first bytes of a new samping cycle are filled with 0 and the actual data is shifted backwards. This behaviour seems to be related to the jitter. I am not sure which of the modules is responsible for the problem, timer, ADC or DMA.
    #3
    Murton Pike Systems
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/02/26 10:44:32 (permalink)
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    I dont know if its relevant to pic32mz but I have had problems with A2D on pic32mx.
    If I try to read a2d port fast I get i.e. 2,2,4,4,6,6,8,8 instead of 2,3,4,5,6,7,8
    If you look in the errata for pic32 it says to limit a2d sample rate to below 500KHz.
    I found using the interrupt flag on a2d if I skipped an interrupt every time I got good data.
     
    The only other way around it I found was a software digital filter


    void smooth()
    {
    int cx;
    int sm1;
    int sm2;
    int sm3;
    int sm4;


    for (cx=0;cx<scopebufferlength-4;cx++)
    {
    sm1=scopebuffer[cx];
    sm2=scopebuffer[cx+1];
    sm3=scopebuffer[cx+2];
    sm4=scopebuffer[cx+3];
    scopebuffer[cx]=(sm1+sm2+sm3+sm4)/4;
    }
    }

    #4
    boiler
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/02/26 12:28:49 (permalink)
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    Thanks for your answere. The MZ (EFH) should be able to do a lot of more and in the errata sheet is no issue listed.
     
    I think I've narrow down the issue, it looks like these artifacts are "bus collisions". When I only run the chain described above to capture samples I get a nearly perfect result. This means that I cannot run my application in "parallel". Is there any way to capture such hick ups? Is there an overview how ADC sampling via DMA will be affected by other events or on which "lines they are connected" to get information about such collisions?
     
    Best Mario
    #5
    Murton Pike Systems
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/02/26 12:42:13 (permalink)
    4 (1)
    If I remember correctly when using DMA you have to be wary of the cache.
    The buffer it reads to should be coherent.

    unsigned short __attribute__((coherent)) scopebuffercoherent[scopebufferlength];

    #6
    boiler
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/03/02 05:29:51 (permalink)
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    Tried it with coherent attribute - no change. sad: sad
     
     
    #7
    boiler
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    Re: PIC32MZ ADC DMA OC unsteady sample amount 2021/03/04 04:09:37 (permalink)
    4 (1)
    I've priorized all my ISR new and the issue is gone Smile: Smile
    #8
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