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Hot!MCP2518FD spi read access

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2021/02/04 01:07:40 (permalink)

MCP2518FD spi read access

I am working on a design which uses the MCP2518FD for receiving CAN messages.
The "MCP25XXFD CAN FD Controller Module Family Reference Manual" states:
"Before reading a Receive Message Object, the application must check that the RX FIFO is not empty by reading the CiFIFOSTAm register."
My question is: what is the impact if the RX FIFO is read via SPI even though it actually _is_ empty?
Is it only that the host might read inconsistent data or is there the risk that CAN frames are lost as the MCP2518 fails to store them internally?
Background: I want the host to perform the SPI-accesses by DMA, unconditionally "dumping" the FIFO area together with the CiFIFOSTAm register; so I would do the CiFIFOSTAm check afterwards by the host (on the dumped data) and throw away the FIFO data in case "empty" is indicated.
WRT the internal implementation of the MCP2518: is this approach feasible or will I violate (undocumented) design assumptions (e.g. host never SPI-reads "empty"-tagged FIFO-Ram)?
Thanks in advance,

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