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Camerart
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2021/01/26 02:19:31 (permalink)
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Master slave PICs SPI errors

Hi,
I'm using an 18LF4620 PIC as MASTER and an 18F4431 PIC as SLAVE, both running on 3.3V.
I'm getting an intermittent error with SPI.
Using a logic analyser, sometime the error is 'The initial (idle) state of the CLK line does not match the settings' or I've seen it start to work then the MISO stays HIGH when it should go LOW, then bad READings.
Any ideas or sulutions please?
Camerart
#1

28 Replies Related Threads

    ric
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    Re: Master slave PICs SPI errors 2021/01/26 02:41:58 (permalink)
    +1 (1)
    How are they connected together?
    E.g. are they on the same PCB, or is there a cable between them?
    The most likely cause of intermittent errors is noise on the CLK line. Glitches or ringing.

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    #2
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 02:59:09 (permalink)
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    ric
    How are they connected together?
    E.g. are they on the same PCB, or is there a cable between them?
    The most likely cause of intermittent errors is noise on the CLK line. Glitches or ringing.

    Hi R,
    They are temporarily connected via cables.  It looks as though my next job is redesigning the PCB with SPI tracks.
     
    If I can ask a secondary question?
    Somehow the SLAVE PIC needs to READ a peripheral, so does it need to be TOGGLED to MASTER, and I suppose the SCK between the other MASTER needs temoprarily separating while it is MASTER, does this sound ok?
    Thanks,
    C.
    #3
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 03:00:19 (permalink)
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    P.S they are both on the same PCB
    #4
    ric
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    Re: Master slave PICs SPI errors 2021/01/26 03:10:51 (permalink)
    +1 (1)
    Camerart
    ric
    How are they connected together?
    E.g. are they on the same PCB, or is there a cable between them?
    The most likely cause of intermittent errors is noise on the CLK line. Glitches or ringing.

    Hi R,
    They are temporarily connected via cables.  It looks as though my next job is redesigning the PCB with SPI tracks.

    How long are the cables?
    It's hard to give good answers with vague information.
    It would be a good idea to observe the clock signal at the slave PIC's input with a good oscilloscope.
     

    If I can ask a secondary question?
    Somehow the SLAVE PIC needs to READ a peripheral, so does it need to be TOGGLED to MASTER, and I suppose the SCK between the other MASTER needs temoprarily separating while it is MASTER, does this sound ok?

    Do you mean another device on the same SPI bus?
    Theoretically it is possible to swap which PIC is Master, but you need to get them to cooperate with each other, and work out how all the CS pins will be driven. It would probably be easier to get the one Master PIC to do the read, then pass that data to the slave PIC.
     

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    #5
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 03:47:54 (permalink)
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    ric
    Camerart
    ric
    How are they connected together?
    E.g. are they on the same PCB, or is there a cable between them?
    The most likely cause of intermittent errors is noise on the CLK line. Glitches or ringing.

    Hi R,
    They are temporarily connected via cables.  It looks as though my next job is redesigning the PCB with SPI tracks.

    How long are the cables?
    It's hard to give good answers with vague information.
    It would be a good idea to observe the clock signal at the slave PIC's input with a good oscilloscope.

    If I can ask a secondary question?
    Somehow the SLAVE PIC needs to READ a peripheral, so does it need to be TOGGLED to MASTER, and I suppose the SCK between the other MASTER needs temoprarily separating while it is MASTER, does this sound ok?

    Do you mean another device on the same SPI bus?
    Theoretically it is possible to swap which PIC is Master, but you need to get them to cooperate with each other, and work out how all the CS pins will be driven. It would probably be easier to get the one Master PIC to do the read, then pass that data to the slave PIC.
     



    The cables are approx 6inches long.
     
    There are only 2x PICs on the PCB.
    The 18LF4620 is always a MASTER
    The 18F4431 is firstly a SLAVE to the 4620, but READs a quadrature encoder.
    It is also needed as an overflow for memory, so I want it to READ a peripheral, then do a calculation, then this DATA plus the QEI DATA then needs to go to the 4620 MASTER.
    I got the idea, that with a signal track between the PICs, the 4431 could switch between it being a MASTER or SLAVE.
    C.
    #6
    Jerry Messina
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    Re: Master slave PICs SPI errors 2021/01/26 04:58:18 (permalink)
    +1 (1)
    If I were you I'd use a different scheme other than SPI... either a uart or even I2C would be simpler.
    By the time you're done adding all the extra handshaking/sync signals between the two to try and make master/slave reliable you've used up a bunch of resources.
     
    SPI slave buffering (or the lack of) on the older pics leaves a lot to be desired.
     
    #7
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 05:02:59 (permalink)
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    Jerry Messina
    If I were you I'd use a different scheme other than SPI... either a uart or even I2C would be simpler.
    By the time you're done adding all the extra handshaking/sync signals between the two to try and make master/slave reliable you've used up a bunch of resources.
     
    SPI slave buffering (or the lack of) on the older pics leaves a lot to be desired.
     


    Hi J,
    This project has been developing for a few years, now, and at the beginning, I chose SPI, so all of the peripherals, are SPI, so it is too late to change :(
    Thanks, C.
     
    #8
    oliverb
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    Re: Master slave PICs SPI errors 2021/01/26 06:06:28 (permalink)
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    So do you have more than just two PICs connected back-to-back then?
     
    If you want the slave device to read a peripheral then I think it will need a second SPI interface. This could be "soft SPI/bitbang" though, as for a blocking master implementation there isn't much advantage to hard SPI over soft.
     
    Potentially you could "turn the port round", but then the master would need to know how long to relinquish the bus for, which could be challenging. Also the out and in pins will be the wrong way round, you could deliberately reverse the peripheral but that would mean the master couldn't access it. Alternatively turn off the port and use bitbang so you can transmit on the "in" pin and recieve on "out".
     
    post edited by oliverb - 2021/01/26 06:16:42
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    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 06:42:37 (permalink)
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    Deleted.
    post edited by Camerart - 2021/01/26 06:59:24
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    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 06:47:13 (permalink)
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    Hi R,
    I replied again to #5 with oscilloscope images, but I don't know what happed, I'll try again.
    These are of CLK and MISO
    C
     
     
    post edited by Camerart - 2021/01/26 06:49:52

    Attached Image(s)

    #11
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/26 06:58:34 (permalink)
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    oliverb
    So do you have more than just two PICs connected back-to-back then?
     
    If you want the slave device to read a peripheral then I think it will need a second SPI interface. This could be "soft SPI/bitbang" though, as for a blocking master implementation there isn't much advantage to hard SPI over soft.
     
    Potentially you could "turn the port round", but then the master would need to know how long to relinquish the bus for, which could be challenging. Also the out and in pins will be the wrong way round, you could deliberately reverse the peripheral but that would mean the master couldn't access it. Alternatively turn off the port and use bitbang so you can transmit on the "in" pin and recieve on "out".
     


    Hi O,


    No only 2x PICs.  I can see problems ahead so, at the moment, it seems an earlier suggestion may be best.  To have 2x MASTERS READing their own peripherals, and the MASTER2, sends back the DATA to MASTER1 via UART.
    C
    post edited by Camerart - 2021/01/26 07:00:50
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    Camerart
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    Re: Master slave PICs SPI errors 2021/01/27 04:49:10 (permalink)
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    ric
    The most likely cause of intermittent errors is noise on the CLK line. Glitches or ringing.

    Hi R,
    The oscilloscope at the 4431 end shows, the CLK and MOSI as expected, but the MISO shows the errors.
    The errors improve if the MISO line between the PICs is disconnected, but still error.
    C.
    #13
    ric
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    Re: Master slave PICs SPI errors 2021/01/27 05:04:47 (permalink)
    +2 (2)
    Your DSO traces show interference on MISO, like there are two devices trying to drive that signal.
    Maybe you have multiple CE liines asserted at the same time.
    There is also signs of overshoot on the CLK signal in the third trace.
    You should set your DSO sampling to "Peak Detect", not "AUTO".
     

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    #14
    oliverb
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    Re: Master slave PICs SPI errors 2021/01/27 06:10:40 (permalink)
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    It really does look like two devices with very different drive capabilities driving the same bus doesn't it, I seem to be seeing 4 different levels.
     
    I thought the spikes on the third trace looked like they were on the data not the clock.
     
    There's a faint sign of a runt pulse on the middle plot's clock but it seems too small to be significant.
     
    #15
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/27 06:31:01 (permalink)
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    Hi R and O,
    Can you explain what you mean 'two devices driving the the signal, please?
     
    The programs are only between two PICs.
     
    I'm wondering if what you are noticing is shadows from the previous frame, as I stopped the Oscilloscope?
     
    I'm going to try to clarify my understanding if SPI, and try a few more tests, which I'll post.
    Is there any test you advise me to do?
    C
    #16
    Camerart
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    Re: Master slave PICs SPI errors 2021/01/27 08:27:40 (permalink)
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    Hi,
    The master normally has other peripherals on the SPI bus, and I left a barometer/altimeter connected, but not address by a CS in the program.
    When this was removed all of the tests worked ok, and when it was back on they failed as before.  As this is intermittent, I'll try some more tests.
    C
    #17
    ric
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    Re: Master slave PICs SPI errors 2021/01/27 12:19:55 (permalink)
    +1 (1)
    Camerart
    The master normally has other peripherals on the SPI bus, and I left a barometer/altimeter connected, but not address by a CS in the program.
    When this was removed all of the tests worked ok, and when it was back on they failed as before.

    As I said in post#14:
    "Maybe you have multiple CE liines asserted at the same time."
     
    Almost certainly this is caused by the other CE signal getting asserted when it shouldn't be.
    This could be caused by setting and clearing pins by addressing a PORTx register when you should always write to a LATx register.
    (I have to use generic names, as you have not revealed what pins the CE outputs are on your PIC).
    Only ever use the PIC's PORTx registers for reading pins, not writing.
     

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    Camerart
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    Re: Master slave PICs SPI errors 2021/01/28 01:45:51 (permalink)
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    ric
    Camerart
    The master normally has other peripherals on the SPI bus, and I left a barometer/altimeter connected, but not address by a CS in the program.
    When this was removed all of the tests worked ok, and when it was back on they failed as before.

    As I said in post#14:
    "Maybe you have multiple CE liines asserted at the same time."
     
    Almost certainly this is caused by the other CE signal getting asserted when it shouldn't be.
    This could be caused by setting and clearing pins by addressing a PORTx register when you should always write to a LATx register.
    (I have to use generic names, as you have not revealed what pins the CE outputs are on your PIC).
    Only ever use the PIC's PORTx registers for reading pins, not writing.
     


    Hi R,
    I'm guessing that asserted means in the programs, but only 1x CS is addressed in the programs, so I left it connected, I misunderstood.
     
    The programs were written for me, to explain, how HW works as apposed the SW, which I have used up to now, so I'm not yet familiar with it.  Here are the programs, they ae written in the only language I know 'BASIC' I hope you can read them. 
     
    I'll try to understand what you mean by PORTX registers.
    C
    post edited by Camerart - 2021/01/28 03:28:12
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    ric
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    Re: Master slave PICs SPI errors 2021/01/28 02:02:49 (permalink)
    +2 (2)
    Camerart
    I'm guessing that asserted means in the programs, but only 1x CS is addressed in the programs, so I left it connected, I misunderstood.

    "Asserted" means a signals is "driven to the active state".
    If you have multiple slaves connected to an SPI bus, then each one must have its own CE signal, and only one of them should ever be driven to the active state.
     
    This program only has one SS output, which is PORTD.2 (that should have been LATD.2, not PORTD.
     

    The programs were written for me, to explain, how HW works as apposed the SW, which I have used up to now, so I'm not yet familiar with it. 

    Whoever wrote this program does not understand SPI.
    The SS signal is not being asserted until AFTER the data has been written to SSPBUF. That is wrong.
     

    I'll try to understand what you mean by PORTX registers.

    "PORTx" is a generic way of describing PORTA, PORTB, PORTC and so on.
    "LATx" is a way of describing LATA, LATB, LATC, etc.
    It's a way of distinguishing between the PORT registers and the LAT registers when you don't know which one.
     
    Back to your SS signal. If you only have one, then you can NOT have more than one SPI device connected to your PIC.
    To connect more than one, you need multiple SS pins, one for each device.
    That is what controls which slave is allowed to drive the MISO wire.
     
    Note, I am using "CS", "CE", and "SS" interchangeably. They all mean the same thing.
    post edited by ric - 2021/01/28 02:07:02

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    #20
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