EBI peripheral DMA anyone see a problem with this.
So I have moved along with my design and got to the point of realizing that an FPGA or CPLD with IO is going to have to sit on the other side of my PIC controller.
So again I have a timer that will trigger a DMA channel that will send 8 bytes of data.
8 Data output ->FPGA input
3 Address line->FPGA input
WR------------->FPGA to latch the 8 registers inside
So basically the FPGA will have 8 registers that I need to write from the PIC. At first I thought ok... PMP should work. But then thinking about it, I thought the busy in the PMP is going to be the problem as well as the address auto increment. I maybe wrong so if that is the case please advise.
The I thought about the 100 pin PIC32MZ EF series and I could map the FPGA in memory and each timer pop do memory to memory with auto increment on both side.
Does anyone see a problem with this?