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Hot!PIC32MZ Interrupt Disable Latency Questions

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nxtaudio
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2021/01/16 12:17:09 (permalink)
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PIC32MZ Interrupt Disable Latency Questions

I realized today that there is a fairly long latency between when you disable an interrupt using the IEC*CLR registers, and when the interrupt actually becomes disabled.
 
It required 6 Nop() calls (which is 6 SSNOP instructions) in order to make sure that the interrupt was truly disabled before proceeding with my critical section code.
 
My code:
void data_get(uint8_t *d1, uint8_t *d2)
{
  IEC4CLR = _IEC4_I2C2MIE_MASK;
  Nop(); Nop(); Nop();
  Nop(); Nop(); Nop();

  *d1 = m_d1;
  *d2 = m_d2;

  IEC4SET = _IEC4_I2C2MIE_MASK;
}

 
Without those Nop() calls, I was sometimes getting inconsistent values for d1 and d2, if the interrupt that sets m_d1 and m_d2 occurred at exactly the wrong time.
 
So make sure sufficient time exists between disabling an interrupt and doing any critical section stuff.
 
My questions:
 
1. Where is this latency documented?  I couldn't find anything in the datasheet or compiler documentation.
2. Is 6 SSNOPs always enough or should i use more?
3. Is there a better way of checking to see that the interrupt has actually been disabled?  I suspect that just reading back the register may not be sufficient.
4. Is this delay time the same for all peripherals, or does it vary?
 
Now, I eventually changed this function to pack both variables into a single uint16 so I could access them atomically without disabling interrupts at all.  But that's not always possible.
 
Thanks!
 
 
post edited by nxtaudio - 2021/01/16 17:37:56
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5 Replies Related Threads

    nxtaudio
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    Re: PIC32MZ Interrupt Disable Latency Questions 2021/01/19 21:47:28 (permalink)
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    Sorry for the bump.
     
    Has anyone run into this issue of there being a delay between when you disable an interrupt and when it actually gets disabled?
     
    I'd just like to know where this time is specified.
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    andersm
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    Re: PIC32MZ Interrupt Disable Latency Questions 2021/01/20 00:32:52 (permalink)
    4.5 (2)
    Some really old threads touching on the subject: https://www.microchip.com/forums/m821595.aspx https://www.microchip.com/forums/m797764.aspx
     
    I don't think the latency is explicitly documented anywhere. I guess in the interrupt disable case you have to account for the inherent latency of all write instructions, and then drain the pipeline, which would add up to about six cycles.
    #3
    moser
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    Re: PIC32MZ Interrupt Disable Latency Questions 2021/01/20 08:33:43 (permalink)
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    I have seen a similar problem, and I agree, that the pipeline is probably the issue.
     
    I killed it by using SYNC instructions. One _sync() after disabling the interrupt. And when I change the shared variable outside of the interrupt, I had another _sync() before enabling the interrupt. Since _sync() also has a memory barrier, it enforces a real read from memory after the first SYNC, and a real write to memory before the second SYNC.
     
    PLIB_INT_SourceDisable(INT_ID_0,INT_SOURCE_MYINT);
    _sync();
    // read, write, or read+write shared variables here.
    _sync();
    PLIB_INT_SourceEnable(INT_ID_0,INT_SOURCE_MYINT);

     
     
    However, be warned: I don't know if this is a correct or good way of doing it, but for me it worked very well.
    #4
    Mysil
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    Re: PIC32MZ Interrupt Disable Latency Questions 2021/01/20 09:13:24 (permalink)
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    Hi,
    But also be aware that if a interrupt have already been triggered, and interrupt processing have started,
    then disabling will not have much effect.
    Interrupt processing will be completed or superseded, depending upon the relative priority.
     
        Mysil
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    nxtaudio
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    Re: PIC32MZ Interrupt Disable Latency Questions 2021/01/23 13:04:09 (permalink)
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    Thanks everyone for the insights. 
     
    In addition to the pipeline, I think there is some clock domain crossing going on when writing the register, and also when reacting to the interrupt signal (even if that signal is internal).  That will take an extra cycle or so whenever it happens.
    #6
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