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AnsweredHot!How to interpret Pin Allocation Tables and PPS ?

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iLuke
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2021/01/14 15:37:03 (permalink)
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How to interpret Pin Allocation Tables and PPS ?

Hello, 
 
I am working on a project that requires the use of 2 UARTS. I have found the device PIC18F26Q10 that has 2 UARTs and the other features I require. I have noticed that in the pin allocation tables for the 28-pin device there is no mention for tx2/rx2 pins. However the PPS peripheral can map these signals to any pin in ports B and C. 
 
Does the pin allocation table show the default POR io mappings that can be overidden with PPS? 
 
Below is a copy of the datasheet : 
https://eu.mouser.com/datasheet/2/268/PIC18F26_45_46_Q10_Data_Sheet_40001996E-1947979.pdf
 
Thanks
#1
ric
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 16:04:58 (permalink)
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iLuke
I have noticed that in the pin allocation tables for the 28-pin device there is no mention for tx2/rx2 pins. However the PPS peripheral can map these signals to any pin in ports B and C.

It's probably an unintentional omission in the datasheet.
Note, default assigments are only for PPS inputs, PPS outputs always have to be programmed by the user.
Have you tried it on a real chip to confirm the second USART is fully useable?
 

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dan1138
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 16:38:40 (permalink)
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Using data sheet DS40001996E as the reference:
 
Table 17-1 (starts on page 287) describes the default PPS input assignments.
EUSART2 uses RB7 as the default RX2 input. There is no PPS assignment for the TX2 output pin.
 
The output latch bit for each PORT pin is the default PPS assignment for outputs.
 
What this means is that all the PPS pins for a function block should always be configured regardless of what the power on defaults are.
#3
ric
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 16:48:20 (permalink)
+1 (1)
OP is complaining about the "Pin Allocation Tables", specifically "Table 3. 28-Pin Allocation Table" on page 7, which only lists "TX1/CK1" and "DT1" in the PPS OUT row for "EUSART".
"Table 4. 40/44-Pin Allocation Table" on page 10 lists "TX1/CK1", "DT1", "TX2/CK2", and "DT2"
 

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blue_led
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 18:31:02 (permalink)
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28 pin version silicon die must be same as 40 with some parts disabled ( pins ) so mapping must be as 40 pin version ( literal )
post edited by blue_led - 2021/01/14 18:40:23
#5
ric
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 18:45:22 (permalink)
+1 (1)
blue_led
28 pin version silicon die must be same as 40 with some parts disabled ( pins ) so mapping must be as 40 pin version ( literal )

I don't see how it can be the same die, when the allowed PPS settings are different on the 40 pin chips.

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dan1138
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/14 19:14:54 (permalink)
+1 (1)
ric
It's probably an unintentional omission in the datasheet.

I think ric is correct in this observation.
 
The DS40001996E data sheet is very confused. It appears to be a hash up of documentation for 28-pin parts that have only one EUSART and the other parts that all have two EUSARTs.
 
You would think after 5 revisions (A to E) Microchip would have these data sheet issues fixed.
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iLuke
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 03:05:10 (permalink)
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I haven't and can't test this out yet becuase I need to built the PCB first.
 
ric
OP is complaining about the "Pin Allocation Tables", specifically "Table 3. 28-Pin Allocation Table" on page 7, which only lists "TX1/CK1" and "DT1" in the PPS OUT row for "EUSART".
"Table 4. 40/44-Pin Allocation Table" on page 10 lists "TX1/CK1", "DT1", "TX2/CK2", and "DT2"
 

 
Precise ric. So should I trust the pin allocation table and assume that UART 2 in not implemented ? Or should I trust the PPS tables and assume that UART 2 is implemented ? It's very unclear from the datasheet. 
 
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iLuke
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 03:29:36 (permalink)
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Further "Table 1.  Devices included in this data sheet" on page 4 of the datasheet, state for PIC18F26Q10 devices, 2 EUSARTs are available. It seems that this part number comes only in 28pin packages and therefore both should be usable through PPS. 
#9
ric
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 03:36:39 (permalink)
+1 (1)
iLuke
 So should I trust the pin allocation table and assume that UART 2 in not implemented ? Or should I trust the PPS tables and assume that UART 2 is implemented ? It's very unclear from the datasheet. 

As I already stated, I think it's an error in the pin allocation table, as everything else points to UART2 being present.
The proof obviously is to try it on a real chip.
 
 

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hexreader
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 05:53:31 (permalink) ☼ Best Answerby iLuke 2021/01/15 06:24:46
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I can confirm that 2 UARTs are available. Test code is below:
 
If I comment out the two lines for Rx PPS allocation, the code still works the same, which leads me to conclude that default pins are RB7 for Rx 2, RC7 for Rx1.
 
What is the best way to post code without the forum software mangling it please?
// simple UART test for PIC18F26Q10
// 8 MHz 2-pin crystal x4PLL for 32MHz clock
// Tested on EasyPIC v7 dev board

// Status 15 January 2021
// - UART 1 RC6 Tx, RC7 Rx - OK so far
// - UART 2 RB6 Tx, RB7 Rx - OK so far

// Rx PPS settings are commented out, as the code matches the default settings
// be sure to power PIC down after commenting out PPS settings - old setting survives reset, but not power down

// PIC18F26Q10 Configuration Bit Settings
// CONFIG1L
#pragma config FEXTOSC = HS // External Oscillator mode Selection bits (HS (crystal oscillator) above 8 MHz; PFM set to high power)
#pragma config RSTOSC = EXTOSC_4PLL// Power-up default value for COSC bits (EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits)

// CONFIG1H
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled)
#pragma config CSWEN = OFF // Clock Switch Enable bit (The NOSC and NDIV bits cannot be changed by user software)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)

// CONFIG2L
#pragma config MCLRE = EXTMCLR // Master Clear Enable bit (MCLR pin (RE3) is MCLR)
#pragma config PWRTE = ON // Power-up Timer Enable bit (Power up timer enabled)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (Low power BOR is disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

// CONFIG2H
#pragma config BORV = VBOR_190 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 1.90V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = OFF // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence))
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled)

// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

// CONFIG4H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config SCANE = ON // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)
#pragma config LVP = OFF // Low Voltage Programming Enable bit (HV on MCLR/VPP must be used for programming)

// CONFIG5L
#pragma config CP = OFF // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)
#pragma config CPD = OFF // DataNVM Memory Code Protection bit (DataNVM code protection disabled)

// CONFIG5H

// CONFIG6L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

// CONFIG6H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)


#define _XTAL_FREQ 32000000

#include <xc.h>
#include <stdio.h>

// initialise PPS map as desired - be sure to set PPS1WAY = OFF in configuration settings
void PPS_Init(void){
    
    RC6PPS = 0x09; // UART 1 Tx RC6 output (options are PORT B and PORT C)
// RX1PPS = 0x17; // UART 1 Rx RC7 input (options are PORT B and PORT C)
    RB6PPS = 0x0b; // UART 2 Tx RB6 output (options are PORT B and PORT C)
// RX2PPS = 0x0f; // UART 2 Rx RB7 input (options are PORT B and PORT C)
}

// initialise IO ports
void IO_Init(void){

    LATA = 0; // all low
    LATB = 0; // all low
    LATC = 0; // all low
    ANSELA = 0; // all digital
    ANSELB = 0; // all digital
    ANSELC = 0; // all digital
    TRISA = 0; // all output
    TRISB = 0x80; // RB7 UART2 input, rest output
    TRISC = 0x80; // RC7 UART1 input, rest output
    //ODCONC = 0x40; // Open Drain output for UART 1 output RC6 - be sure to fit 1k pull-up
}

// initialise UART
void UART_Init(void){
    
    RC1STA = 0x90; // Rx enable 8 bit
    TX1STA = 0x20; // Tx enable
    BAUD1CON = 0x08; // 16 bit BRG
    SP1BRG = 0x00cf; // set baud rate - 00cf=9600

    RC2STA = 0x90; // Rx enable 8 bit
    TX2STA = 0x20; // Tx enable
    BAUD2CON = 0x08; // 16 bit BRG
    SP2BRG = 0x00cf; // set baud rate - 00cf=9600
    __delay_ms(100); // UART settle time
}

// wait for character to be received from UART
unsigned char chin(void){
  unsigned char err_stat;
  unsigned char ret_char = 0;
  
    while(! ret_char){
        if(PIR3bits.RCIF){ // wait for character to be available
            err_stat = RC1STA; // read errors - not yet used - for later
            ret_char = RC1REG;
        }
        if(PIR3bits.RC2IF){ // wait for character to be available
            err_stat = RC2STA; // read errors - not yet used - for later
            ret_char = RC2REG;
        }
    }
  
    return ret_char; // return the character
}

// send character to UART
void putch(unsigned char uout_char){
    
    while( ! PIR3bits.TXIF); // wait for Tx ready
    TX1REG = uout_char; // send the character

    while( ! PIR3bits.TX2IF); // wait for Tx ready
    TX2REG = uout_char; // send the character
}

// program starts here
int main(int argc, char** argv){
  unsigned char temp_char;
  
    PPS_Init(); // map peripherals to pins
    IO_Init(); // initialise IO ports
    UART_Init(); // initialise UART
    
    printf("\r\nUART test 15 January 2021\r\n\n");
    
    while(1){ // main loop
        temp_char = chin(); // wait for character to be received
        putch(temp_char); // send same character out
    }
}

 
post edited by hexreader - 2021/01/15 06:26:09

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iLuke
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 06:25:14 (permalink)
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Thank you hexreader for your input! 
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hexreader
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Re: How to interpret Pin Allocation Tables and PPS ? 2021/01/15 06:34:18 (permalink)
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Let's try attaching text file in the hope of preserving formatting....
 
 

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