dsPIC33CH128MP505 duty cycle not updating

Hello. I have an dsPIC33CH128MP505 with a potentiometer attached to adc channel 4 with pwm1 trigger which is connected via software to pwm module 2. I want to increase or decrease the duty cycle using the potentiometer. When I first configured registers it worked nicely, however now the PG2DC no longer updates its value and the PWM DC has the value that I set at initialization time. PRINT is a define for a function with variable arguments to print to serial, while mcu_init(); holds initialization functions. I also created some defines to help me with register configurations. If you like I can give you the whole project, I just don't understand how it is possible for the PGxDC register not to update. 
 

#ifndef CONFIGBITS_H
#define CONFIGBITS_H

// DSPIC33CH128MP505 Configuration Bit Settings

// 'C' source line config statements



// FSEC
#pragma config BWRP = OFF // Boot Segment Write-Protect bit (Boot Segment may be written)
#pragma config BSS = DISABLED // Boot Segment Code-Protect Level bits (No Protection (other than BWRP))
#pragma config BSEN = OFF // Boot Segment Control bit (No Boot Segment)
#pragma config GWRP = OFF // General Segment Write-Protect bit (General Segment may be written)
#pragma config GSS = DISABLED // General Segment Code-Protect Level bits (No Protection (other than GWRP))
#pragma config CWRP = OFF // Configuration Segment Write-Protect bit (Configuration Segment may be written)
#pragma config CSS = DISABLED // Configuration Segment Code-Protect Level bits (No Protection (other than CWRP))
#pragma config AIVTDIS = OFF // Alternate Interrupt Vector Table bit (Disabled AIVT)

// FBSLIM
#pragma config BSLIM = 0x1FFF // Boot Segment Flash Page Address Limit bits (Enter Hexadecimal value)

// FSIGN

// FOSCSEL
#pragma config FNOSC = PRI // Oscillator Source Selection (Internal Fast RC (FRC) Oscillator with postscaler)
#pragma config IESO = OFF // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FOSC
#pragma config POSCMD = EC // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = OFF // OSC2 Pin Function bit (OSC2 is clock output)
#pragma config FCKSM = CSECMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)
#pragma config XTCFG = G0 // XT Config (24-32 MHz crystals)
#pragma config XTBST = DISABLE // XT Boost (Boost the kick-start)

// FWDT
#pragma config RWDTPS = PS8192 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config WINDIS = ON // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config FWDTEN = ON // Watchdog Timer Enable bit (WDT enabled in hardware)

// FICD
#pragma config ICS = PGD2 // ICD Communication Channel Select bits (Communicate on PGC2 and PGD2)
#pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled)

// FDMTIVTL
#pragma config DMTIVTL = 0xFFFF // Dead Man Timer Interval low word (Enter Hexadecimal value)

// FDMTIVTH
#pragma config DMTIVTH = 0xFFFF // Dead Man Timer Interval high word (Enter Hexadecimal value)

// FDMTCNTL
#pragma config DMTCNTL = 0xFFFF // Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Enter Hexadecimal value)

// FDMTCNTH
#pragma config DMTCNTH = 0xFFFF // Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF) (Enter Hexadecimal value)

// FDMT
#pragma config DMTDIS = OFF // Dead Man Timer Disable bit (Dead Man Timer is Disabled and can be enabled by software)

// FDEVOPT
#pragma config ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF // Alternate I2C2 Pin bit (I2C2 mapped to SDA2/SCL2 pins)
#pragma config SMBEN = SMBUS // SM Bus Enable (SMBus input threshold is enabled)
#pragma config SPI2PIN = DEDICATED // SPI2 Pin Select bit (SPI2 uses I/O remap (PPS) pins)

// FALTREG
#pragma config CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)
#pragma config CTXT3 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits (Not Assigned)
#pragma config CTXT4 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits (Not Assigned)

// FMBXM
#pragma config MBXM0 = S2M // Mailbox 0 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM1 = S2M // Mailbox 1 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM2 = S2M // Mailbox 2 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM3 = S2M // Mailbox 3 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM4 = S2M // Mailbox 4 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM5 = S2M // Mailbox 5 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM6 = S2M // Mailbox 6 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM7 = S2M // Mailbox 7 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM8 = S2M // Mailbox 8 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM9 = S2M // Mailbox 9 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM10 = S2M // Mailbox 10 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM11 = S2M // Mailbox 11 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM12 = S2M // Mailbox 12 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM13 = S2M // Mailbox 13 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM14 = S2M // Mailbox 14 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))
#pragma config MBXM15 = S2M // Mailbox 15 data direction (Mailbox register configured for Master data read (Slave to Master data transfer))

// FMBXHS1
#pragma config MBXHSA = MBX15 // Mailbox handshake protocol block A register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block A)
#pragma config MBXHSB = MBX15 // Mailbox handshake protocol block B register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block B)
#pragma config MBXHSC = MBX15 // Mailbox handshake protocol block C register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block C)
#pragma config MBXHSD = MBX15 // Mailbox handshake protocol block D register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block D)

// FMBXHS2
#pragma config MBXHSE = MBX15 // Mailbox handshake protocol block E register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block E)
#pragma config MBXHSF = MBX15 // Mailbox handshake protocol block F register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block F)
#pragma config MBXHSG = MBX15 // Mailbox handshake protocol block G register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block G)
#pragma config MBXHSH = MBX15 // Mailbox handshake protocol block H register assignment (MSIxMBXD15 assigned to mailbox handshake protocol block H)

// FMBXHSEN
#pragma config HSAEN = OFF // Mailbox A data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSBEN = OFF // Mailbox B data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSCEN = OFF // Mailbox C data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSDEN = OFF // Mailbox D data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSEEN = OFF // Mailbox E data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSFEN = OFF // Mailbox F data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSGEN = OFF // Mailbox G data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)
#pragma config HSHEN = OFF // Mailbox H data flow control protocol block enable (Mailbox data flow control handshake protocol block disabled.)

// FCFGPRA0
#pragma config CPRA0 = MSTR // Pin RA0 Ownership Bits (Master core owns pin.)
#pragma config CPRA1 = MSTR // Pin RA1 Ownership Bits (Master core owns pin.)
#pragma config CPRA2 = MSTR // Pin RA2 Ownership Bits (Master core owns pin.)
#pragma config CPRA3 = MSTR // Pin RA3 Ownership Bits (Master core owns pin.)
#pragma config CPRA4 = MSTR // Pin RA4 Ownership Bits (Master core owns pin.)

// FCFGPRB0
#pragma config CPRB0 = MSTR // Pin RB0 Ownership Bits (Master core owns pin.)
#pragma config CPRB1 = MSTR // Pin RB1 Ownership Bits (Master core owns pin.)
#pragma config CPRB2 = MSTR // Pin RB2 Ownership Bits (Master core owns pin.)
#pragma config CPRB3 = MSTR // Pin RB3 Ownership Bits (Master core owns pin.)
#pragma config CPRB4 = MSTR // Pin RB4 Ownership Bits (Master core owns pin.)
#pragma config CPRB5 = MSTR // Pin RB5 Ownership Bits (Master core owns pin.)
#pragma config CPRB6 = MSTR // Pin RB6 Ownership Bits (Master core owns pin.)
#pragma config CPRB7 = MSTR // Pin RB7 Ownership Bits (Master core owns pin.)
#pragma config CPRB8 = MSTR // Pin RB8 Ownership Bits (Master core owns pin.)
#pragma config CPRB9 = MSTR // Pin RB9 Ownership Bits (Master core owns pin.)
#pragma config CPRB10 = MSTR // Pin RB10 Ownership Bits (Master core owns pin.)
#pragma config CPRB11 = MSTR // Pin RB11 Ownership Bits (Master core owns pin.)
#pragma config CPRB12 = MSTR // Pin RB12 Ownership Bits (Master core owns pin.)
#pragma config CPRB13 = MSTR // Pin RB13 Ownership Bits (Master core owns pin.)
#pragma config CPRB14 = MSTR // Pin RB14 Ownership Bits (Master core owns pin.)
#pragma config CPRB15 = MSTR // Pin RB15 Ownership Bits (Master core owns pin.)

// FCFGPRC0
#pragma config CPRC0 = MSTR // Pin RC0 Ownership Bits (Master core owns pin.)
#pragma config CPRC1 = MSTR // Pin RC1 Ownership Bits (Master core owns pin.)
#pragma config CPRC2 = MSTR // Pin RC2 Ownership Bits (Master core owns pin.)
#pragma config CPRC3 = MSTR // Pin RC3 Ownership Bits (Master core owns pin.)
#pragma config CPRC4 = MSTR // Pin RC4 Ownership Bits (Master core owns pin.)
#pragma config CPRC5 = MSTR // Pin RC5 Ownership Bits (Master core owns pin.)
#pragma config CPRC6 = MSTR // Pin RC6 Ownership Bits (Master core owns pin.)
#pragma config CPRC7 = MSTR // Pin RC7 Ownership Bits (Master core owns pin.)
#pragma config CPRC8 = MSTR // Pin RC8 Ownership Bits (Master core owns pin.)
#pragma config CPRC9 = MSTR // Pin RC9 Ownership Bits (Master core owns pin.)
#pragma config CPRC10 = MSTR // Pin RC10 Ownership Bits (Master core owns pin.)
#pragma config CPRC11 = MSTR // Pin RC11 Ownership Bits (Master core owns pin.)
#pragma config CPRC12 = MSTR // Pin RC12 Ownership Bits (Master core owns pin.)
#pragma config CPRC13 = MSTR // Pin RC13 Ownership Bits (Master core owns pin.)
#pragma config CPRC14 = MSTR // Pin RC14 Ownership Bits (Master core owns pin.)
#pragma config CPRC15 = MSTR // Pin RC15 Ownership Bits (Master core owns pin.)

// FCFGPRD0
#pragma config CPRD0 = MSTR // Pin RD0 Ownership Bits (Master core owns pin.)
#pragma config CPRD1 = MSTR // Pin RD1 Ownership Bits (Master core owns pin.)
#pragma config CPRD2 = MSTR // Pin RD2 Ownership Bits (Master core owns pin.)
#pragma config CPRD3 = MSTR // Pin RD3 Ownership Bits (Master core owns pin.)
#pragma config CPRD4 = MSTR // Pin RD4 Ownership Bits (Master core owns pin.)
#pragma config CPRD5 = MSTR // Pin RD5 Ownership Bits (Master core owns pin.)
#pragma config CPRD6 = MSTR // Pin RD6 Ownership Bits (Master core owns pin.)
#pragma config CPRD7 = MSTR // Pin RD7 Ownership Bits (Master core owns pin.)
#pragma config CPRD8 = MSTR // Pin RD8 Ownership Bits (Master core owns pin.)
#pragma config CPRD9 = MSTR // Pin RD9 Ownership Bits (Master core owns pin.)
#pragma config CPRD10 = MSTR // Pin RD10 Ownership Bits (Master core owns pin.)
#pragma config CPRD11 = MSTR // Pin RD11 Ownership Bits (Master core owns pin.)
#pragma config CPRD12 = MSTR // Pin RD12 Ownership Bits (Master core owns pin.)
#pragma config CPRD13 = MSTR // Pin RD13 Ownership Bits (Master core owns pin.)
#pragma config CPRD14 = MSTR // Pin RD14 Ownership Bits (Master core owns pin.)
#pragma config CPRD15 = MSTR // Pin RD15 Ownership Bits (Master core owns pin.)

// FCFGPRE0
#pragma config CPRE0 = MSTR // Pin RE0 Ownership Bits (Master core owns pin.)
#pragma config CPRE1 = MSTR // Pin RE1 Ownership Bits (Master core owns pin.)
#pragma config CPRE2 = MSTR // Pin RE2 Ownership Bits (Master core owns pin.)
#pragma config CPRE3 = MSTR // Pin RE3 Ownership Bits (Master core owns pin.)
#pragma config CPRE4 = MSTR // Pin RE4 Ownership Bits (Master core owns pin.)
#pragma config CPRE5 = MSTR // Pin RE5 Ownership Bits (Master core owns pin.)
#pragma config CPRE6 = MSTR // Pin RE6 Ownership Bits (Master core owns pin.)
#pragma config CPRE7 = MSTR // Pin RE7 Ownership Bits (Master core owns pin.)
#pragma config CPRE8 = MSTR // Pin RE8 Ownership Bits (Master core owns pin.)
#pragma config CPRE9 = MSTR // Pin RE9 Ownership Bits (Master core owns pin.)
#pragma config CPRE10 = MSTR // Pin RE10 Ownership Bits (Master core owns pin.)
#pragma config CPRE11 = MSTR // Pin RE11 Ownership Bits (Master core owns pin.)
#pragma config CPRE12 = MSTR // Pin RE12 Ownership Bits (Master core owns pin.)
#pragma config CPRE13 = MSTR // Pin RE13 Ownership Bits (Master core owns pin.)
#pragma config CPRE14 = MSTR // Pin RE14 Ownership Bits (Master core owns pin.)
#pragma config CPRE15 = MSTR // Pin RE15 Ownership Bits (Master core owns pin.)

// FS1OSCSEL
#pragma config S1FNOSC = FRCDIVN // Oscillator Source Selection (Internal Fast RC (FRC) Oscillator with postscaler)
#pragma config S1IESO = ON // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FS1OSC
#pragma config S1OSCIOFNC = OFF // Slave OSC2 Pin Function bit (OSC2 is clock output)
#pragma config S1FCKSM = CSDCMD // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are disabled)

// FS1WDT
#pragma config S1RWDTPS = PS1048576 // Run Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1RCLKSEL = LPRC // Watchdog Timer Clock Select bits (Always use LPRC)
#pragma config S1WINDIS = ON // Watchdog Timer Window Enable bit (Watchdog Timer operates in Non-Window mode)
#pragma config S1WDTWIN = WIN25 // Watchdog Timer Window Select bits (WDT Window is 25% of WDT period)
#pragma config S1SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Post Scaler select bits (1:1048576)
#pragma config S1FWDTEN = ON // Watchdog Timer Enable bit (WDT enabled in hardware)

// FS1ICD
#pragma config S1ICS = PGD2 // ICD Communication Channel Select bits (Communicate on PGC2 and PGD2)
#pragma config S1ISOLAT = ON // Isolate the Slave core subsystem from the master subsystem during Debug (The slave can operate (in debug mode) even if the SLVEN bit in the MSI is zero.)
#pragma config S1NOBTSWP = OFF // BOOTSWP Instruction Enable/Disable bit (BOOTSWP instruction is disabled)

// FS1DEVOPT
#pragma config S1ALTI2C1 = OFF // Alternate I2C1 Pin bit (I2C1 mapped to SDA1/SCL1 pins)
#pragma config S1SPI1PIN = PPS // S1 SPI1 Pin Select bit (Slave SPI1 uses I/O remap (PPS) pins)
#pragma config S1SSRE = ON // Slave Slave Reset Enable (Slave generated resets will reset the Slave Enable Bit in the MSI module)
#pragma config S1MSRE = ON // Master Slave Reset Enable (The master software oriented RESET events (RESET Op-Code, Watchdog timeout, TRAP reset, illegalInstruction) will also cause the slave subsystem to reset.)

// FS1ALTREG
#pragma config S1CTXT1 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits (Not Assigned)
#pragma config S1CTXT2 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits (Not Assigned)
#pragma config S1CTXT3 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits (Not Assigned)
#pragma config S1CTXT4 = OFF // Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits (Not Assigned)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#endif /* CONFIGBITS_H */

void osc_init(void) 
{
    // FRCDIV FRC/1; PLLPRE 1; DOZE 1:8; DOZEN disabled; ROI disabled; 
    CLKDIV = 0x3601;
    // PLLFBDIV 150; 
    PLLFBD = 0x96;
    // TUN Center frequency; 
    OSCTUN = 0x00;
    // POST1DIV 1:4; VCODIV FVCO/4; POST2DIV 1:1; 
    PLLDIV = 0x41;
    // APLLEN disabled; FRCSEL FRC; APLLPRE 1:1; 
    ACLKCON1 = 0x101;
    // APLLFBDIV 150; 
    APLLFBD1 = 0x96;
    // APOST1DIV 1:4; APOST2DIV 1:1; AVCODIV FVCO/4; 
    APLLDIV1 = 0x41;
    // IOLOCK disabled; 
    RPCON = 0x00;
    // CF no clock failure; NOSC FRCDIV; CLKLOCK unlocked; OSWEN Switch is Complete; 
    //__builtin_write_OSCCONH((uint8_t) (0x02));
    //__builtin_write_OSCCONL((uint8_t) (0x00));
    
    // Wait for Clock switch to occur
    while (OSCCONbits.OSWEN!= 0);
}

#define PWM_MCLK_SEL PCLKCONbits.MCLKSEL
#define PWM_CLK_DIV_SEL PCLKCONbits.DIVSEL

#define PWM2_PER PG2PER
#define PWM2L_DC PG2TRIGB
#define PWM2H_DC PG2DC
#define PWM2_ENABLE PG2CONLbits.ON
#define PWM2_CLK_SEL PG2CONLbits.CLKSEL
#define PWM2_RES PG2CONLbits.HREN
#define PWM2_MOD_SEL PG2CONLbits.MODSEL
#define PWM2_H_EN PG2IOCONHbits.PENH
#define PWM2_L_EN PG2IOCONHbits.PENL
#define PWM2_OUT_MODE PG2IOCONHbits.PMOD

//clock selection
#define PWM_M_CLK_DIV_CLK (0b10)
#define PWM_M_CLK_MCLKSEL (0b01)
#define PWM_CLK_DIV_1_16 (0b11)
//resolution
#define PWM_HIGH_RES (1)
#define PWM_STD_RES (0)
//pwm mode selection
#define PWM_IND_EDGE_PWM_DO (0b010)
//pwm output mode
#define PWM_IND_MODE (0b01)

void hspwm_init(void)
{
    //COMMON SETTINGS
    PWM_CLK_DIV_SEL = PWM_CLK_DIV_1_16;
    PWM_MCLK_SEL = REG_DEFAULT_VALUE;
    //PWM 2
    PWM2_ENABLE = CLEAR;
    PWM2_CLK_SEL = PWM_M_CLK_DIV_CLK;
    PWM2_MOD_SEL = PWM_IND_EDGE_PWM_DO;
    PWM2_OUT_MODE = PWM_IND_MODE;
    PWM2_RES = PWM_STD_RES;
    PWM2_H_EN = SET;
    PWM2_L_EN = SET;
    PG2CONHbits.MDCSEL = 0;
    //Set at 4ms
    PWM2_PER = 10000;
    PWM2H_DC = 6500;
    PWM2L_DC = 7500;
    PWM2_ENABLE = SET;
}

void hspwm2H_dc(uint16_t dc)
{
    PWM2H_DC = dc;
}

void hspwm2L_dc(uint16_t dc)
{
    PWM2L_DC = dc;
}

int main(void) 
{ 
    time1 = TIMER_TICKS_PER_SECOND;
    time2 = 0;
    timeNow = 0;
    state = 0;

    mcu_init();
    
    PRINT("Starting...");

    while(1) {

        timeNow = timer_get_time();
        if(timeNow - time1 > TIMER_TICKS_PER_SECOND) {
            PRINT("ADC AN4 READING: %d", adc_getChData(4));
           PG2DC = adc_getChData(4);

            if(state) {
                led_boardLed(ON);
            } else {
                led_boardLed(OFF);
            }
            
            PRINT("hello world %d", myVar);
            state = !state;
            time1 = timer_get_time();
            myVar++;
        }
        WDTCONH = 0x5743;
    }
}

The pwm module is much more complicate on cH/CK chips than FJ/EP series .When updating PWM duty/frequency ,you have to set UPDREQ 
Before you update duty cycle ,make sure the UPDTRG[1:0] in PGxEVTL has been correctly set .
The UPDTRG is default to 0b00 , which means you  must set the UPDREQ bit (PGxSTAT[3]) manually, by so ,you have to set UPDREQ  =1 after you write to PGxDC.
 
suggested code :
void hspwm2L_dc(uint16_t dc)
{
PWM2L_DC = dc;
PG2STATbits.UPDREQ = 1;
}
 
 
Or set UPDTRG  =  0b01 ; // A write of the PGxDC register automatically sets the UPDREQ bit