• AVR Freaks

Hot!Synplify O-2018.09-SP1 removing logic blocks

Author
avivA W.
New Member
  • Total Posts : 3
  • Reward points : 0
  • Joined: 2020/03/20 14:13:03
  • Location: 0
  • Status: offline
2021/01/08 12:55:20 (permalink)
0

Synplify O-2018.09-SP1 removing logic blocks

We are synthesizing an RTG4 design with Synplify Pro and Premier, version O-2018.09-SP1. For no reason we can figure out, entire blocks of logic are being removed by the tool. We thought it might have something to do with the tool not understanding our divided-down clocks or synchronously deasserted resets. But blocks are still removed when we take that stuff out. We tried attribute syn_noprune on the affected blocks, and Synplify ignores the attributes and continues to remove the blocks.
 
Has anyone experienced this? Is this a Synplify bug that is fixed in a later version? Would a different synthesis tool give us better results? If so, what does Microsemi recommend?
 
Aviva Williams
#1

5 Replies Related Threads

    RISC
    Super Member
    • Total Posts : 5998
    • Reward points : 0
    • Status: offline
    Re: Synplify O-2018.09-SP1 removing logic blocks 2021/01/08 15:15:54 (permalink)
    2 (1)
    Hi,
    This is a users forum...
    If you want to get some support on Microsemi products, you should use the official Microchip technical support website : http://www.microchip.com/support
    Regards

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #2
    nivinpauly
    New Member
    • Total Posts : 7
    • Reward points : 0
    • Joined: 2020/03/23 05:33:38
    • Location: 0
    • Status: offline
    Re: Synplify O-2018.09-SP1 removing logic blocks 2021/01/11 02:24:47 (permalink)
    0
    Hi Aviva,
     
    I dont think thats a bug in the tool. Synplify can remove blocks due to different reasons. The synthesis tool removes logic as part of optimization. Following are some reasons behind logic optimization:
    1. Logic block is in inadvertent reset due to possible error in code. 
    2. Outputs dont change. That is, they are remaining at a constant value. Synplify will remove the entire block and drive the output from constant. 
    3. Logic block does not have any external output port. 


    Please review your design and see if any of above issues are there in your design. 
     
    Synplify optimizes the design by pruning unused/duplicate registers/nets/blocks. You can manually
    control the amount of auto optimization by applying the following directives.
    • *syn_keep ensures that if a wire is kept during synthesis and that there are no optimizations cross
    the wire. This directive is usually used to break unwanted optimizations and to ensure manually
    created replications. It works only on nets and combinational logic.
    • *syn_preserve ensures that registers are not optimized away.
    • *syn_noprune ensures that a black box is not optimized away when its outputs are unused (that is,
    when its outputs do not drive any logic).


    In case you are not able to resolve the issue, please create a case at http://soc.microsemi.com/Portal/DPortal.aspx?v=1 for FPGA related issues.
     
    Regards,
    Nivin Paul
     
    #3
    avivA W.
    New Member
    • Total Posts : 3
    • Reward points : 0
    • Joined: 2020/03/20 14:13:03
    • Location: 0
    • Status: offline
    Re: Synplify O-2018.09-SP1 removing logic blocks 2021/01/11 10:57:24 (permalink)
    0
    Thank you, Nivin. I spent a lot of time verifying that #1 is not the case. It may be something like #2 because we get these warnings on outputs of the affected blocks:
    @N: BN362 :"/cgi/cgi-fpga-lowfsc/fpga/submodules/cgi-fpga-common/ram/
    ram_dualport_generic_wrapper.sv":86:2:86:7|Removing sequential instance
    u_le_reg_wrapper_secondary.waddr[31] (in view: work.lp_fpga_top(verilog)) of type
    view:PrimLib.dffr(prim) because it does not drive other instances.

    We get them on like an entire address bus, though, which does not make any sense from a design perspective and is not the behavior seen in simulation.
    I would consider a bottoms-up synthesis approach, doing each block separately and then bringing them together-- clearly Synplify is having some trouble understanding our design-- but I don't think Synplify supports such a methodology.
    But this does give me an idea to synthesize smaller chunks of the design to try to figure out where the problems are starting...
    post edited by avivale1124 - 2021/01/11 10:58:55
    #4
    nivinpauly
    New Member
    • Total Posts : 7
    • Reward points : 0
    • Joined: 2020/03/23 05:33:38
    • Location: 0
    • Status: offline
    Re: Synplify O-2018.09-SP1 removing logic blocks 2021/01/21 21:29:26 (permalink)
    0
    Hi Aviva, 
     
    Is your issue resolved? 
     
    Regards,
    Nivin Paul
    #5
    avivA W.
    New Member
    • Total Posts : 3
    • Reward points : 0
    • Joined: 2020/03/20 14:13:03
    • Location: 0
    • Status: offline
    Re: Synplify O-2018.09-SP1 removing logic blocks 2021/01/29 13:04:50 (permalink)
    4 (1)
    No, I don't think it is resolved yet. But I am only helping the primary FPGA designer so I need to work with her to determine whether blocks are still being removed and to try to figure out why.
     
    In the meantime I discovered that Synplify Premier supports hierarchical synthesis so I have been trying that to see if we get different/better results.
    #6
    Jump to:
    © 2021 APG vNext Commercial Version 4.5