I dont think thats a bug in the tool. Synplify can remove blocks due to different reasons. The synthesis tool removes logic as part of optimization. Following are some reasons behind logic optimization:
1. Logic block is in inadvertent reset due to possible error in code.
2. Outputs dont change. That is, they are remaining at a constant value. Synplify will remove the entire block and drive the output from constant.
3. Logic block does not have any external output port.
Please review your design and see if any of above issues are there in your design.
Synplify optimizes the design by pruning unused/duplicate registers/nets/blocks. You can manually
control the amount of auto optimization by applying the following directives.
ensures that if a wire is kept during synthesis and that there are no optimizations cross
the wire. This directive is usually used to break unwanted optimizations and to ensure manually
created replications. It works only on nets and combinational logic.
ensures that registers are not optimized away.
ensures that a black box is not optimized away when its outputs are unused (that is,
when its outputs do not drive any logic).
In case you are not able to resolve the issue, please create a case at http://soc.microsemi.com/Portal/DPortal.aspx?v=1
for FPGA related issues.