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Helpful ReplyHot!PIC24EP128MC206

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edmondog
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2020/11/28 11:28:23 (permalink)
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PIC24EP128MC206

I made a very simple application to test a PIC24EP128MC206 cpu, but I can't make it work.
Here is the code:

// PIC24EP128MC206 Configuration Bit Settings

// 'C' source line config statements

// FICD
#pragma config ICS = PGD1               // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
#pragma config JTAGEN = OFF             // JTAG Enable bit (JTAG is disabled)

// FPOR
#pragma config ALTI2C1 = OFF            // Alternate I2C1 pins (I2C1 mapped to SDA1/SCL1 pins)
#pragma config ALTI2C2 = OFF            // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
#pragma config WDTWIN = WIN25           // Watchdog Window Select bits (WDT Window is 25% of WDT period)

// FWDT
#pragma config WDTPOST = PS32768        // Watchdog Timer Postscaler bits (1:32,768)
#pragma config WDTPRE = PR128           // Watchdog Timer Prescaler bit (1:128)
#pragma config PLLKEN = OFF             // PLL Lock Enable bit (Clock switch will not wait for the PLL lock signal.)
#pragma config WINDIS = OFF             // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
#pragma config FWDTEN = OFF             // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)

// FOSC
#pragma config POSCMD = NONE            // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = ON            // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
#pragma config IOL1WAY = OFF            // Peripheral pin select configuration (Allow multiple reconfigurations)
#pragma config FCKSM = CSECME           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are enabled)

// FOSCSEL
#pragma config FNOSC = FRC              // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config PWMLOCK = ON             // PWM Lock Enable bit (Certain PWM registers may only be written after key sequence)
#pragma config IESO = ON                // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)

// FGS
#pragma config GWRP = OFF               // General Segment Write-Protect bit (General Segment may be written)
#pragma config GCP = OFF                // General Segment Code-Protect bit (General Segment Code protect is Disabled)

#include <xc.h>

int main(void)
{
    ClrWdt();
    RCONbits.SWDTEN = 0;
    TRISG=0;
    TRISAbits.TRISA10=0;
    LATG=0xFF;
    PORTG=0xFF;
    LATAbits.LATA10=1;
    PORTAbits.RA10=1;
    while(1)
    {
        ClrWdt();
    }
    return 0;
}
 
I can program the chip, but nothing happens on the G port pins and if I try to run the debuger i get this message:
Currently loaded firmware on PICkit 3
Firmware Suite Version.....01.54.00
Firmware type..............dsPIC33E/24E

Programmer to target power is enabled - VDD = 3,250000 volts.
Target device PIC24EP128MC206 found.
Device Revision ID = 4008

Device Erased...

Programming...

The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x3ff
configuration memory
Programming/Verify complete
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.


The cpu is fully powered, 10k res to VDD on reset pin, 25uF cap on VCAP pin
I must be missing something, but I can't find what...
Attached the project  and the eagle files.
HELP!!!!
 
#1
MBedder
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Re: PIC24EP128MC206 2020/11/28 12:18:38 (permalink)
4.5 (2)
So you're suggesting us download and install Eagle just for viewing your lousy schematics, don't you?
#2
Mysil
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Re: PIC24EP128MC206 2020/11/28 18:34:23 (permalink)
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Hi,
What pins (pin numbers) are the programming signals PGC and PGD connected to?
 
    Mysil
#3
edmondog
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Re: PIC24EP128MC206 2020/11/28 23:41:55 (permalink)
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Sorry. It's the fist time I use the forum in 10 years.... Until now I always solved these problems by myself.
The pgd is connected to pin 18 PGED1/AN5/C1IN1-/RP35/RB3
and pgc is connected to pin 17 PGEC1/AN4/C1IN1+/RPI34/RB2
and the fist line of code declares:
#pragma config ICS = PGD1               // ICD Communication Channel Select bits (Communicate on PGEC1 and PGED1)
The chip gets actually programmed so I excluded that common mistake.
The problem is that the chip can't be debugged, so I think I must have some mistake in the clock source, but I can't see what.
The debugger I am using is a PICKit3 that works quite fine with all the other boards I have.
The voltage is provided by the PICKit3, but nothing chages if I power the chip externally. The result is always the same:
Programmer to target power is enabled - VDD = 3,250000 volts.
Target device PIC24EP128MC206 found.
Device Revision ID = 4008

Device Erased...

Programming...

The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x3ff
configuration memory
Programming/Verify complete
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.
If I dump the processor memory I get the code and it looks ok.
The fuses I used for defining the clock are as follows:
// FOSC
#pragma config POSCMD = NONE            // Primary Oscillator Mode Select bits (Primary Oscillator disabled)
#pragma config OSCIOFNC = ON            // OSC2 Pin Function bit (OSC2 is general purpose digital I/O pin)
#pragma config IOL1WAY = OFF            // Peripheral pin select configuration (Allow multiple reconfigurations)
#pragma config FCKSM = CSECME           // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are enabled)

// FOSCSEL
#pragma config FNOSC = FRC              // Oscillator Source Selection (Internal Fast RC (FRC))
#pragma config PWMLOCK = ON             // PWM Lock Enable bit (Certain PWM registers may only be written after key sequence)
#pragma config IESO = ON                // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
So I can't find where my nistake is...
post edited by edmondog - 2020/11/28 23:50:49

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#4
RISC
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Re: PIC24EP128MC206 2020/11/29 02:37:46 (permalink)
2 (1)
Hi,
There are much more registers to initialize....
e.g. some pins which are analog/digital capables are always analog on reset and you need to initialize them in digital mode...
To get started, I suggest you use MCC plugin for MPLAB X . It will help you initialize this chip and get started.
BTW, to output a value on a PORT you must use LAT (reserve PORT for input mode only)
Regards 
post edited by RISC - 2020/11/29 08:55:27

For support make sure to check first here : http://microchipdeveloper.com
There are hundreds of PIC, AVR, SAM...which one do YOU use ?
#5
Mysil
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Re: PIC24EP128MC206 2020/11/29 06:29:05 (permalink)
2 (1)
Hi,
Could you try the following experiment:
Remove all configuration settings,
except:  #pragma config FWDTEN = OFF 
 
To see if you can get into the debugger with default configuration bits, with only Watchdog timer disabled.
 
Regards,
    Mysil
 
#6
edmondog
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Re: PIC24EP128MC206 2020/11/29 07:52:32 (permalink)
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Mysil
Hi,
Could you try the following experiment:
Remove all configuration settings,
except:  #pragma config FWDTEN = OFF 
 
To see if you can get into the debugger with default configuration bits, with only Watchdog timer disabled.
 
Regards,
    Mysil
 


No, the behaviour is just the same.
 
Target voltage detected
Target device PIC24EP128MC206 found.
Device Revision ID = 4008

Device Erased...

Programming...

The following memory area(s) will be programmed:
program memory: start address = 0x0, end address = 0x3ff
configuration memory
Programming/Verify complete
The target device is not ready for debugging. Please check your configuration bit settings and program the device before proceeding. The most common causes for this failure are oscillator and/or PGC/PGD settings.


#7
edmondog
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Re: PIC24EP128MC206 2020/11/29 10:17:36 (permalink)
0
I reinstalled MplabX to be shure to have the last version of everything and it did also install a new version of firmware on my PICKit3, then I made a new project using MCC with all the default values + PORTG output and high.
Still the same issues.
1) The chip gets programmed correctly or, at least, the PICKit3 thinks so.
2) No output on PORTG
3) No debug starting
#8
T Yorky
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Re: PIC24EP128MC206 2020/11/29 10:53:31 (permalink)
3 (2)
Just a note. You can program on any of the program pins. But you must have the pin allocation matched in order to use the debugger.
Haven't checked all your stuff but fail safe is to use FRC. Debugger will always run on start. Put a break point at first instruction in main to check operation prior to any code changing clocks.
T Yorky.
#9
edmondog
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Re: PIC24EP128MC206 2020/11/29 12:05:05 (permalink)
3 (1)
I got where the problem came from!
I had a large capacitor (330uF) on AVDD separated from VDD by a 33 Ohm resistor.
With a 10 uF cap the cpu starts without any problem.
Don't ask me why...
Anyway thank you evreybody for your support.
Edo.
#10
ric
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Re: PIC24EP128MC206 2020/11/29 12:13:59 (permalink) ☄ Helpfulby edmondog 2020/11/29 22:40:35
5 (3)
edmondog
...
I had a large capacitor (330uF) on AVDD separated from VDD by a 33 Ohm resistor.
With a 10 uF cap the cpu starts without any problem.
Don't ask me why...

Because that would make AVDD reach legal voltages MUCH later than VDD.
You must make sure those voltages are never more than about 0.3V apart.
A schottky diode to quickly conduct from VDD to AVDD would have helped.
Yet again a problem due to an unusual schematic that we never got to see.
 

I also post at: PicForum
Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
NEW USERS: Posting images, links and code - workaround for restrictions.
To get a useful answer, always state which PIC you are using!
#11
dan1138
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Re: PIC24EP128MC206 2020/11/29 15:20:37 (permalink)
3.5 (2)
@edmondog,
 
This code works for me:
/*
 * File:   main.c
 * Author: dan1138
 * Target: PIC24EP128MC206
 * Compiler: XC18 v1.60
 * IDE: MPLABX v5.45
 *
 *                                                                                 PIC24EP128MC206
 *                 +---------------------+                 +---------------------+                 +---------------------+                 +---------------------+
 *           <>  1 : RA7                 :   ICD_PGC <> 17 : RB2/PGEC1/AN4       :           <> 33 : RA4/RP20            :           <> 49 : RB9/RP41            :
 *           <>  2 : RB14/RPI46          :   ICD_PGD <> 18 : RB3/PGED1/AN5       :           <> 34 : RA9/RPI25           :           <> 50 : RC6/RP54            :
 *           <>  3 : RB15/RPI47          :       3v3 <> 19 : AVDD                :           <> 35 : RC3/RPI51           :           <> 51 : RC7/RP55            :
 *           <>  4 : RG6/RP118           :       GND <> 20 : AVSS                :           <> 36 : RC4/RPI52           :           <> 52 : RC8/RP56            :
 *           <>  5 : RG7/RPI119          :           <> 21 : RC0/AN6             :           <> 37 : RC5/RPI53           :           <> 53 : RD5                 :
 *           <>  6 : RG8/RP120           :           <> 22 : RC1/AN7             :       3v3 <> 38 : VDD                 :           <> 54 : RD6                 :
 *   ICD_VPP <>  7 : MCLRn               :           <> 23 : RC2/AN8             :           <> 39 : RC12/OSC1           :           <> 55 : RC9/RP57            :
 *           <>  8 : RG9/RPI121          :           <> 24 : RC11/AN11           :           <> 40 : RC15/OSC2           :      10uF <> 56 : VCAP                :
 *       GND <>  9 : VSS                 :       GND <> 25 : VSS                 :       GND <> 41 : VSS                 :       3v3 <> 57 : VDD                 :
 *       3v3 <> 10 : VDD                 :       3v3 <> 26 : VDD                 :           <> 42 : RD8                 :           <> 58 : RF0/RPI96           :
 *           <> 11 : RA12/RPI28/AN10     :           <> 27 : RE12/AN12           :           <> 43 : RB5/PGED2/RP37      :           <> 59 : RF1/RP97            :
 *           <> 12 : RA11/RPI27/AN9      :           <> 28 : RE13/AN13           :           <> 44 : RB6/PGEC2/RP38      :           <> 60 : RB10/RP42           :
 *           <> 13 : RA0//AN0            :           <> 29 : RE14/RPI94/AN14     :           <> 45 : RC10/RPI58          :           <> 61 : RB11/RP43           :
 *           <> 14 : RA1//AN1            :           <> 30 : RE15/RPI95/AN15     :           <> 46 : RB7/RP39/INT0       :           <> 62 : RB12/RPI44          :
 *           <> 15 : RB0/PGED3/RPI32/AN2 :           <> 31 : RA8/RPI24           :           <> 47 : RC13                :           <> 63 : RB13/RPI45          :
 *           <> 16 : RB1/PGEC3/RPI33/AN3 :           <> 32 : RB4/RP36            :           <> 48 : RB8/RP40            :           <> 64 : RA10                :
 *                 +---------------------+                 +---------------------+                 +---------------------+                 +---------------------+
 *                                                                                    TQFP-64
 * Created on November 29, 2020, 11:27 AM
 */

#pragma config ICS = PGD1, JTAGEN = OFF, ALTI2C1 = OFF, ALTI2C2 = OFF
#pragma config WDTWIN = WIN25, WDTPOST = PS32768, WDTPRE = PR128
#pragma config PLLKEN = ON, WINDIS = OFF, FWDTEN = OFF, POSCMD = NONE
#pragma config OSCIOFNC = ON, IOL1WAY = OFF, FCKSM = CSECMD, FNOSC = FRC
#pragma config PWMLOCK = OFF, IESO = ON, GWRP = OFF, GCP = OFF

#include "xc.h"

int main(void)
{
    
    ANSELA = 0;
    ANSELB = 0;
    ANSELC = 0;
    ANSELE = 0;
    
    TRISG=0;
    TRISAbits.TRISA10=0;
    LATG=0xFFFF;
    PORTG=0xFFFF;
    LATAbits.LATA10=1;
    PORTAbits.RA10=1;

    for(;;)
    {
        LATAbits.LATA10^=1;
    }
    return 0;
}

#12
edmondog
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Re: PIC24EP128MC206 2020/11/29 22:47:28 (permalink)
2 (1)
ric
edmondog
...
I had a large capacitor (330uF) on AVDD separated from VDD by a 33 Ohm resistor.
With a 10 uF cap the cpu starts without any problem.
Don't ask me why...

Because that would make AVDD reach legal voltages MUCH later than VDD.
You must make sure those voltages are never more than about 0.3V apart.
A schottky diode to quickly conduct from VDD to AVDD would have helped.
Yet again a problem due to an unusual schematic that we never got to see.
 


Thank you, Ric.
Honestly there was no reason in placing such a big capacitor there except that I got two of them on my desk...
I just hope this could be of some help for someone else as lazy as I am!
#13
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