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Hot!Issue with PIC32MZDAS EBI and 256K SRAM

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MaccorFW
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2020/11/19 06:20:21 (permalink)
4 (1)

Issue with PIC32MZDAS EBI and 256K SRAM

Need some help in the getting the EBI interface to fully work.

We have an EBI interface test board with a PIC32MZ DAS MCU and 256kx16 SRAM.
The test code is simply a modified version of the one supplied in the EBI data sheet.
The issue is the code will only work for the first 64K, even though CS0 is configured to span 256K address locations.
If higher virtual addresses are written or read, used the MPLABX is stuck-- although it will eventually halt if so commanded.

Is the problem the H3 configuration?
The SRAM does have 18 address lines, a 16 bit interface, and one CS pin.

Also, the 32 bit pointer virtual memory variable value advances by 4 for every addr_ptr++, so how does that translate into actual address bits for the SRAM?
Is 0xC000 0000 to 0xC000 0004 advancing the SRAM address bus from 0x0 0000 0000 to 0x0 0000 0001 or to 0x0 0000 0004??

Thanks




    while ( true )
    {
        /* Maintain state machines of all polled MPLAB Harmony modules. */
        SYS_Tasks ( );
        
        // write        
        // Set start address        
        addr_ptr=(u_32_BIT *)SRAM_VIRT_ADDR_CS0;
        val2=0x0001;  // unsigned 16 bit
        
        //for (loop=0; loop <RAM_SIZE/4; loop++)
        for (loop=0; loop <0x10000; loop++)    // loop: unsigned 32 bit        
        {
          *addr_ptr++= val2++;
          Nop();
          Nop();
          
        }    
        
        Nop();

        //Read/verify
        // Set start address       
        addr_ptr=(u_32_BIT *)SRAM_VIRT_ADDR_CS0;
        val2=0x0001;        
        //for (loop=0; loop <RAM_SIZE/4; loop++)
        for (loop=0; loop <0x10000; loop++)            
        {

          val= *addr_ptr++;     // val: unsigned 16 bit      
          if (val != val2) //0xAA55AA55)
          {
              count++;
              Nop();
          }
          val2++;

        }          
        
        Nop(); // Write/Read success
        
    }

    /* Execution should not come here during normal operation */

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#1

7 Replies Related Threads

    Morce323
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2020/11/19 13:36:39 (permalink)
    4 (1)
    I dont have personal experience with connecting SRAM using EBI - and datasheets I have quickly checked dont mention addressing mode.

    However addr_ptr seems to be uint32_t pointer, which is obviously 4 bytes long, so incrementing it causes its address to increment by 4.

    Your RAM is organised into 256k 16bit words, and 64k * 4 equals 256k, which probably wont be coincidence.

    My guess is address 0x0000 gives you first 16 bit word and 0x0001 gives you second. I would try something like uint16_t val1 = *((uint16_t*)(SRAM_VIRT_ADDR_CS0 + 1));

    However as I said I dont have personal experience with EBI, not quite sure if it can handle such unaligned (from cpus perspective) access. Probably wont work. You should experiment a bit with addressing. It might also be possible to treat each word as 8 bit only at the expense of reducing your capacity to half.
    post edited by Morce323 - 2020/11/19 15:32:21
    #2
    MaccorFW
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2020/12/28 14:21:43 (permalink)
    0
    Thanks for the feedback.
    This is a new design, and it turned out the first board has some solder connection issues..
    The second board worked ok.
     
    #3
    MaccorFW
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2021/01/20 10:50:49 (permalink)
    0
    The earlier post seems to have been a bit premature.
    We added an EBI interface to another board, and I found the EBI signals were not working correctly.
    So I went back to test board, and found things were not correct there either, signal wise.
     
    I've verified the EBICS0, EBIBS0, EBIWE, and EBIOE signals get to the SRAM with some direct port code.
    And all are set in the H3 configurator to their appropriate port pins.
     
    Configurator
    Configurator
    The only active external signals on the EBI interface are EBICS and EBIOE.
    EBIOE is active for reads AND as writes..
     
    The present version of the test code writes to 32 locations and reads back & verifies 32 times.
    In addition to the lack of EBIWE or EBIBS0 pin signals, there are only 8 selects, not the 32 asked for.
    Running only the writes or only the reads results in 8 selects.
    Running the full write & read operation still results in 8 selects.
     
    And the most odd part:
    The physical SRAM is not being accessed, but the read & verify does. 
    So the EBI peripheral is apparently only accessing some internal memory. 
    I've even taken the project to have no EBI or DDR periherals, and the write/read test still passes.
     
    The only controllable part of the peripheral that looks to be working is changing the various wait states values.
     
    Any suggestions to get the EBI working?
    Does the PIC32MZ2064DA device have a functional EBI interface?
     
    MPLABX ver 5.45
    XC32 ver 2.50
     
     
    Thanks.
     
     
     

              #define SRAM_VIRT_ADDR_CS0 0xC0000000 // EBI base in virtual memory (KSEG2)

             u_32_BIT loop, count;
             u_32_BIT *addr_ptr;
             u_16_BIT val, val2;


              // write        
              // Set start address        
              addr_ptr=(u_32_BIT *)SRAM_VIRT_ADDR_CS0;
              val2=0x0001;

              for (loop=0; loop <0x0020; loop++)    
              {
                *addr_ptr++= val2++;
                   
              }

              //Read&verify
              // Set start address       
             addr_ptr=(u_32_BIT *)SRAM_VIRT_ADDR_CS0;
             val2=0x0001;  
             count=0;

            for (loop=0; loop <0x0020; loop++)
            {
              val= *addr_ptr++;          

              if (val != val2)
              {
                  count++;

              }
              val2++;
              val=0;

            }         

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    #4
    cirilo.b
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2021/01/20 13:33:49 (permalink)
    4 (1)
    Did you set up the TLB to work with EBI? What SRAM are you using? You may be fooling yourself and reading/writing the cache rather than the SRAM, especially since you mention that having no EBI gives you the same results; after all the 0xC0.... address is KSEG2 (cacheable).  If you see no attempts to write SRAM it could be because the cache is not being flushed.
    #5
    MaccorFW
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2021/01/21 07:14:46 (permalink)
    0
    Yes, the page the EBI example code is on states at the top it is assumed the TLB is set up, I've not found any documentation on how to so.   The assumption has been that H3 sets that up correctly.  The EBI init code H3 generates are setting the same registers we can set ourselves, nothing I've seen has anything about TLB. 
    Yes, I'd agree the code is likely just talking to the cache.  Yet, there IS some life on two of the EBI pins...
     
     
     
    #6
    cirilo.b
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2021/01/21 14:17:37 (permalink)
    3 (1)
    Assuming the TLB is properly configured, all I can suggest is reading out the PMD register to check that EBI is not disabled, then reading out the EBI registers to check that they are set as expected. The only other thing to check is that there are no other peripherals enabled which use any of the required EBI pins.
    #7
    andersm
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    Re: Issue with PIC32MZDAS EBI and 256K SRAM 2021/01/21 14:47:05 (permalink)
    4 (1)
    The default startup code should set up the TLB for both the EBI and SQI memory regions (__pic32_init_tlb_ebi_sqi, called from crt0).
    #8
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