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Helpful ReplyHot!PIC18F47Q10: Internal pull-up on RC4 (40 DIL package)

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Just4Fun
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2020/10/28 11:13:23 (permalink)
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PIC18F47Q10: Internal pull-up on RC4 (40 DIL package)

Hi,
I'm currently making some tests using a custom board just to get some "confidence" with it.
 
I've noticed on the datasheet (see the attached image for the 40 pins package) that on every GPIO it is possible activate the internal pull-up excerpt for RC4:
 

 
Anyway MCC (from MPLABX) doesn't complain if I set the pull-up for RC4, more based on my tests the pull-up seems to be present on RC4 too.
 
So I'm wondering if I've misunderstood the datasheet or anyone has experienced that (or may be a typo on that page...).
 
BTW: I've read the errata too but there is nothing about it.
 
Regards.
 
 

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#1
mbrowning
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/28 13:16:31 (permalink)
+1 (1)
What datasheet revision are you looking at? I'm not sure mine is the latest, but Rev D shows a "Y" for RC4.
 
edit - I checked and D is the latest.
edit - oops 28pin table has "Y" but 40 pin has "-". As noted below, error in datasheet.
post edited by mbrowning - 2020/10/28 18:08:12
#2
hexreader
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/28 13:23:50 (permalink)
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28 pin table shows a 'Y' for RC4
Registers show pull-up bit for RC4.
 
I reckon it is a datasheet error. The 40 pin table should show a 'Y' not a '-'
 
If I get bored later - I may write simple test code to prove it on real hardware.

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hexreader
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/28 13:53:55 (permalink)
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I got bored pretty quick :)
 
RC4 WPU works just like RC0, 1, 2, 3, 5.
Datasheet should show a 'Y' for RC4 40-pin same as for 28-pin PIC
 
Here is the code that I used (along with a voltmeter) for the test:
// simple test of weak pull-ups on PORTC - Supply = 5 Volts

// Forget RC6 and RC7 - I did not bother to disable UART - so the results are meaningless
// two tests applied
// 1) 10K pull-down on RC0 through RC5 - all voltages show as 0 Volts for 5 seconds, 0.95 Volts for 5 seconds
// 2) less scientific - no pull-downs, but LED + 1K resistor to ground - all LEDs light for 5 seconds, off for 5 seconds

// PIC18F47Q10 Configuration Bit Settings
// 'C' source line config statements
// CONFIG1L
#pragma config FEXTOSC = HS // External Oscillator mode Selection bits (HS (crystal oscillator) above 8 MHz; PFM set to high power)
#pragma config RSTOSC = EXTOSC_4PLL// Power-up default value for COSC bits (EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits)

// CONFIG1H
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled)
#pragma config CSWEN = OFF // Clock Switch Enable bit (The NOSC and NDIV bits cannot be changed by user software)
#pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)

// CONFIG2L
#pragma config MCLRE = EXTMCLR // Master Clear Enable bit (MCLR pin (RE3) is MCLR)
#pragma config PWRTE = ON // Power-up Timer Enable bit (Power up timer enabled)
#pragma config LPBOREN = OFF // Low-power BOR enable bit (Low power BOR is disabled)
#pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

// CONFIG2H
#pragma config BORV = VBOR_190 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 1.90V)
#pragma config ZCD = OFF // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)
#pragma config PPS1WAY = OFF // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence))
#pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config XINST = OFF // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

// CONFIG3L
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = OFF // WDT operating mode (WDT Disabled)

// CONFIG3H
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4L
#pragma config WRT0 = OFF // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
#pragma config WRT4 = OFF // Write Protection Block 4 (Block 4 (010000-013FFFh) not write-protected)
#pragma config WRT5 = OFF // Write Protection Block 5 (Block 5 (014000-017FFFh) not write-protected)
#pragma config WRT6 = OFF // Write Protection Block 6 (Block 6 (018000-01BFFFh) not write-protected)
#pragma config WRT7 = OFF // Write Protection Block 7 (Block 7 (01C000-01FFFFh) not write-protected)

// CONFIG4H
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
#pragma config SCANE = ON // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)
#pragma config LVP = OFF // Low Voltage Programming Enable bit (HV on MCLR/VPP must be used for programming)

// CONFIG5L
#pragma config CP = OFF // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)
#pragma config CPD = OFF // DataNVM Memory Code Protection bit (DataNVM code protection disabled)

// CONFIG5H

// CONFIG6L
#pragma config EBTR0 = OFF // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR4 = OFF // Table Read Protection Block 4 (Block 4 (010000-013FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR5 = OFF // Table Read Protection Block 5 (Block 5 (014000-017FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR6 = OFF // Table Read Protection Block 6 (Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR7 = OFF // Table Read Protection Block 7 (Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks)

// CONFIG6H
#pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

#define _XTAL_FREQ 32000000 // 8MHz 2-pin crystal x4PLL

#include <xc.h>


int main(int argc, char** argv) {
    LATC = 0; // all low
    LATD = 0; // all LEDs off
    ANSELC = 0; // all digital
    TRISC = 0xff; // all input
    ANSELD = 0; // all digital
    TRISD = 0x00; // all output for LEDs

    while(1){
        WPUC = 0xff; //
        LATD = 0x01; // led indicator
        __delay_ms(5000);
        WPUC = 0x00;
        LATD = 0x00; // led indicator
        __delay_ms(5000); // allow time for voltage check
    }
}

 
 

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Mysil
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/28 16:28:06 (permalink) ☄ Helpfulby Just4Fun 2020/10/29 09:28:12
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Hi,
Datasheet revision D, Table 4 for 40/44 pin devices,   DS40002043D-page 9, show the table as in message #1 
 
But register summary section 35,
and detailed register documentation  15.5.23 WPUC  , show all the bits present.
So it seem to me that there may be a mistake in the table on page 9.
 
If the bit is defined in Device support header file, and work when set, then I cannot see any problem using it.
I think this may be stuff for a report to www.microchip.com/support
 
    Mysil
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dan1138
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/28 17:20:59 (permalink)
+1 (1)
On DS40001996D-page 4, Table 1. claims these Devices included in this data sheet PIC18F26Q10, PIC18F45Q10, PIC18F46Q10 but it shows no pull-up for RC4:
 
https://ww1.microchip.com/downloads/en/DeviceDoc/PIC18F26-45-46Q10-Data-Sheet-40001996d.pdf
 
So features present in the controllers we have on hand change when we read a different data sheet.
 
It would seem Schrödinger's cat is now a technical writer at Microchip.
 
This quantum computing is not all it's cracked up to be.
post edited by dan1138 - 2020/10/29 09:59:04
#6
Just4Fun
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/29 09:28:26 (permalink)
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Thanks guys,
I've just opened a case on the support page.
 
Regards.
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upand_at_them
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Re: PIC18F47Q10: Internal pull-up on RC4 (40 DIL package) 2020/10/29 13:00:55 (permalink)
+1 (1)
I've pointed out many datasheet errors to Microchip...They have yet to fix a single one.
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