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Hot!PIC32MX795: SPI master with RX and TX interrupts

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PhreakShow
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2020/10/24 07:06:43 (permalink)
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PIC32MX795: SPI master with RX and TX interrupts

Hey guys.
 
I am using a PIC32MX795F512H with a 1MHz SPI, trying to communicate with slave. Usually there's four bytes in order to read a register, but the length is not fixed to four in general.
 
Right now, it goes like this: Put four bytes in an array, set the number of bytes I want to send and then set the SPI TX IRQ bit. During the ISR, after each byte, I decrement the send counter until it reaches zero, then I disable the TX IRQ. Works like a charm.
 
Additionally, every byte sent also receives one byte because it is SPI. In the same way I want to trigger a RX IRQ, getting the received byte and increasing the index of my RX array.
 
But in a four byte protocol, the RX IRQ only triggers three times. The fourth byte is received after I start to send another frame. I confirmed this behaviour with the debugger.
 
void __ISR(_SPI_2_VECTOR, ipl7)IRQHandler_SPI2(void)
{
 if (INTGetFlag(INT_SOURCE_SPI_RX(SPI_CHANNEL2)))
 {
  gSPIRX[gSPIReceiveCounter++] = SPI2BUF;
  
  IFS1bits.SPI2RXIF = 0;
 }
 
 if (INTGetFlag(INT_SOURCE_SPI_TX(SPI_CHANNEL2)))
 {
  SPI2BUF = gSPITX[gSPISendCounter++];

  if (gSPISendCounter >= gSPISendLength)
  {
   IEC1bits.SPI2TXIE = 0;
   gSPISendCounter = 0;
  }
  IFS1bits.SPI2TXIF = 0;
 }
}

 
Why doesn't the last byte received over the SPI not trigger another RX interrupt?
#1

13 Replies Related Threads

    Jim Nickerson
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 07:29:52 (permalink)
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    What slave device are you using ?
    Maybe the slave requires a request to read the fourth byte and therefore you needd a dummy/null request to fetch the fourth byte
    #2
    PhreakShow
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 07:37:36 (permalink)
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    Actually, the slave does not matter. I have the same behaviour with a KSZ8864 switch. And I see the correct responses with both oscilloscope and logic analyzer. There's four bytes on MOSI, of course at the same time four bytes back on MISO. The last byte on MISO contains the answer, but on my PIC the RX IRQ is not triggered. After sending another frame, I get the last byte from the previous answer frame. 
    #3
    Jim Nickerson
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 08:05:38 (permalink)
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    The attached image is from the KSZ8864 pdf  DS00002229D
    A dummy request is sent to generate the clocks to get the Read Data

     

    Attached Image(s)

    #4
    PhreakShow
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 08:10:00 (permalink)
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    You seem to be missing my point. I see the response on the data line (MISO), where I attached an oscilloscope. 
    But the RX IRQ is not triggered.

    Edit: I send four bytes. That should trigger four RX interrupts, yielding three 0x00 and the last containing the actual data. But the interrupt only trigger three times, and misses the last one.
    post edited by PhreakShow - 2020/10/24 08:13:13
    #5
    Jim Nickerson
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 08:17:06 (permalink)
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    PhreakShow
    After sending another frame, I get the last byte from the previous answer frame. 

    It would seem the slave was waiting for 8 clocks ( the dummy read ) before sending the data.
    #6
    davea
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 09:30:43 (permalink)
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    ww1.microchip.com/downloads/en/DeviceDoc/61106G.pdf
    #7
    PhreakShow
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 11:31:49 (permalink)
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    JANickerson
    It would seem the slave was waiting for 8 clocks ( the dummy read ) before sending the data.



    Even without a slave attached, it would be the same problem. Clocking out four bytes, receiving four bytes. RX IRQ only firing thrice instead of four times. Does not make sense to me?
    #8
    Mysil
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 14:09:22 (permalink)
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    Hi,
    There are a lot of setup options for the SPI peripheral.
    Without a complete program that demonstrate the problem, and can be built and debugged, 
    it may be impossible to be sure about the reason.
     
    See: Short Selfcontained Correct (Compilable) Example:   http://sscce.org/
     
        Mysil
    #9
    davea
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 15:32:10 (permalink)
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    maybe you have to read RX buffer after the last TX byte has transferred out..
    Im not sure what flags it takes to do this  
    but i sure its there (the missing byte)
    post edited by davea - 2020/10/24 15:41:14
    #10
    ric
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 16:22:40 (permalink)
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    JANickerson
    What slave device are you using ?
    Maybe the slave requires a request to read the fourth byte and therefore you needd a dummy/null request to fetch the fourth byte

    Jim, as the OP has been stating, this has absolutely nothing to do with the Slave.
    Transfers are totally controlled by the Master, so it will behave the same with or without the Slave connected at all.
     
    Phreakshow, there are variable settings for how the SPI interrupts work, but you have not revealed how you have set the SPIxCON register.
     

    I also post at: PicForum
    Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
    NEW USERS: Posting images, links and code - workaround for restrictions.
    To get a useful answer, always state which PIC you are using!
    #11
    GeeWhizz
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 19:46:41 (permalink)
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    You are not showing all of your code.  I can't tell if you're setting the Rx interrupt enable flag anywhere.
     
    The symptoms suggest that you're relying on the Tx interrupt being enabled to process received data.
    #12
    davea
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 20:04:23 (permalink)
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    @ric
    do you know when the TXbuf empty flag gets set and you clear it 
    and do not write to spibuffer and exit, leaving it's ISR on 
    will it stop doing TXbuf empty ISR's
    or continuously loop the ISR
    Works like a charm.

    is a little suspect 
     
     
    #13
    ric
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    Re: PIC32MX795: SPI master with RX and TX interrupts 2020/10/24 22:03:44 (permalink)
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    GeeWhizz
    You are not showing all of your code.  I can't tell if you're setting the Rx interrupt enable flag anywhere.

    +1
    This mistake would give the described behaviour.
    As usual, the problem is nearly always in the code that is not posted.
     

    I also post at: PicForum
    Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
    NEW USERS: Posting images, links and code - workaround for restrictions.
    To get a useful answer, always state which PIC you are using!
    #14
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