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Hot!CN interrupt on dsPIC33CK

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GregA
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2020/09/29 13:29:12 (permalink)
2 (1)

CN interrupt on dsPIC33CK

Hello,
i have problem to configure cn imput for have interrupt on rising edge.
The interrupt dont occur, but the CNFx is good
My code:
//init:
_TRISD14 = 1;
_CNPUD14 = 1;
CNCONDbits.CNSTYLE=1;
CNCONDbits.ON=1;
CNEN1Dbits.CNEN1D14=1;
CNEN0Dbits.CNEN0D14=1;
CNFD=0;             //clear change notification
_CNDIP=7;       // priority
IFS1bits.CNCIF = 0;    // Reset change notice interrupt flag
IEC1bits.CNCIE = 1;     // Enable CN interrupts
 
//interrupt:
void __attribute__((__interrupt__,no_auto_psv)) _CNCInterrupt(void)     
{
    if(CNFDbits.CNFD14)
    {
        CNFDbits.CNFD14=0;
    } 
    IFS1bits.CNCIF = 0;      // Clear CN interrupt
}


If i stop the debuging when the imput is change, the CNFDbits.CNFD14 is set.
Thanks
#1

3 Replies Related Threads

    Aussie Susan
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    Re: CN interrupt on dsPIC33CK 2020/09/29 20:32:30 (permalink)
    0
    Probably the fault is in the config settings or the rest of your code - neither of which you show us.
    Susan
    #2
    GregA
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    Re: CN interrupt on dsPIC33CK 2020/09/30 00:20:31 (permalink)
    0
    Ok,
    I isolate my code problem and add configuration in other project in on file, same result:
    For test it i have add breakpoint in interrupt subroutine.
    The CNCIF bit is not set, but CNFD14 is set.
     
    Thanks
     
    #include "xc.h"
    // Configuration bits: selected in the GUI

    // FSEC
    #pragma config BWRP = OFF    //Boot Segment Write-Protect bit->Boot Segment may be written
    #pragma config BSS = DISABLED    //Boot Segment Code-Protect Level bits->No Protection (other than BWRP)
    #pragma config BSEN = OFF    //Boot Segment Control bit->No Boot Segment
    #pragma config GWRP = OFF    //General Segment Write-Protect bit->General Segment may be written
    #pragma config GSS = DISABLED    //General Segment Code-Protect Level bits->No Protection (other than GWRP)
    #pragma config CWRP = OFF    //Configuration Segment Write-Protect bit->Configuration Segment may be written
    #pragma config CSS = DISABLED    //Configuration Segment Code-Protect Level bits->No Protection (other than CWRP)
    #pragma config AIVTDIS = OFF    //Alternate Interrupt Vector Table bit->Disabled AIVT

    // FBSLIM
    #pragma config BSLIM = 8191    //Boot Segment Flash Page Address Limit bits->8191

    // FOSCSEL
    #pragma config FNOSC = FRC    //Oscillator Source Selection->FRC
    #pragma config IESO = ON    //Two-speed Oscillator Start-up Enable bit->Start up device with FRC, then switch to user-selected oscillator source

    // FOSC
    #pragma config POSCMD = NONE    //Primary Oscillator Mode Select bits->Primary Oscillator disabled
    #pragma config OSCIOFNC = ON    //OSC2 Pin Function bit->OSC2 is general purpose digital I/O pin
    #pragma config FCKSM = CSECMD    //Clock Switching Mode bits->Clock switching is enabled,Fail-safe Clock Monitor is disabled
    #pragma config PLLKEN = ON    //PLL Lock Status Control->PLL lock signal will be used to disable PLL clock output if lock is lost
    #pragma config XTCFG = G3    //XT Config->24-32 MHz crystals
    #pragma config XTBST = ENABLE    //XT Boost->Boost the kick-start

    // FWDT
    #pragma config RWDTPS = PS1024    //Run Mode Watchdog Timer Post Scaler select bits->1:1024
    #pragma config RCLKSEL = LPRC    //Watchdog Timer Clock Select bits->Always use LPRC
    #pragma config WINDIS = ON    //Watchdog Timer Window Enable bit->Watchdog Timer in Non-Window mode
    #pragma config WDTWIN = WIN25    //Watchdog Timer Window Select bits->WDT Window is 25% of WDT period
    #pragma config SWDTPS = PS1048576    //Sleep Mode Watchdog Timer Post Scaler select bits->1:1048576
    #pragma config FWDTEN = ON_SW    //Watchdog Timer Enable bit->WDT controlled via SW, use WDTCON.ON bit

    // FPOR
    #pragma config BISTDIS = DISABLED    //Memory BIST Feature Disable->mBIST on reset feature disabled

    // FICD
    #pragma config ICS = PGD2    //ICD Communication Channel Select bits->Communicate on PGC2 and PGD2
    #pragma config JTAGEN = OFF    //JTAG Enable bit->JTAG is disabled
    #pragma config NOBTSWP = DISABLED    //BOOTSWP instruction disable bit->BOOTSWP instruction is disabled

    // FDMTIVTL
    #pragma config DMTIVTL = 0    //Dead Man Timer Interval low word->0

    // FDMTIVTH
    #pragma config DMTIVTH = 0    //Dead Man Timer Interval high word->0

    // FDMTCNTL
    #pragma config DMTCNTL = 0    //Lower 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0

    // FDMTCNTH
    #pragma config DMTCNTH = 0    //Upper 16 bits of 32 bit DMT instruction count time-out value (0-0xFFFF)->0

    // FDMT
    #pragma config DMTDIS = OFF    //Dead Man Timer Disable bit->Dead Man Timer is Disabled and can be enabled by software

    // FDEVOPT
    #pragma config ALTI2C1 = OFF    //Alternate I2C1 Pin bit->I2C1 mONapped to SDA1/SCL1 pins
    #pragma config ALTI2C2 = OFF    //Alternate I2C2 Pin bit->I2C2 mapped to SDA2/SCL2 pins
    #pragma config ALTI2C3 = ON    //Alternate I2C3 Pin bit->I2C3 mapped to ASDA3/ASCL3 pins
    #pragma config SMBEN = SMBUS    //SM Bus Enable->SMBus input threshold is enabled
    #pragma config SPI2PIN = PPS    //SPI2 Pin Select bit->SPI2 uses I/O remap (PPS) pins

    // FALTREG
    #pragma config CTXT1 = OFF    //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits->Not Assigned
    #pragma config CTXT2 = OFF    //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits->Not Assigned
    #pragma config CTXT3 = OFF    //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 3 bits->Not Assigned
    #pragma config CTXT4 = OFF    //Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 4 bits->Not Assigned

    // FBTSEQ
    #pragma config BSEQ = 4095    //Relative value defining which partition will be active after device Reset; the partition containing a lower boot number will be active->4095
    #pragma config IBSEQ = 4095    //The one's complement of BSEQ; must be calculated by the user and written during device programming.->4095

    // FBOOT
    #pragma config BTMODE = SINGLE    //Device Boot Mode Configuration->Device is in Single Boot (legacy) mode

        #define M   50      //= PLLFBDbits.PLLFBDIV;
        #define N1  1       //= CLKDIVbits.PLLPRE;
        #define N2 1        //= PLLDIVbits.POST1DIV;
        #define N3 1        //= PLLDIVbits.POST2DIV;

    void ConfigureOscillator(void)  //frequence interne 100Mhz (maxi))
    {
       /* Disable Watch Dog Timer */
        WDTCONLbits.ON =0;
        
         // FRCDIV FRC/1; PLLPRE 1; DOZE 1:8; DOZEN disabled; ROI disabled;
        CLKDIVbits.PLLPRE=N1;
        CLKDIVbits.DOZE=3;
        PLLFBD = M;
        // TUN Center frequency;
        OSCTUN = 0x00;
        // POST1DIV 1:1; VCODIV FVCO/4; POST2DIV 1:1;
        PLLDIVbits.POST1DIV=N2;
        PLLDIVbits.POST2DIV=N3;
        // APLLEN disabled; FRCSEL FRC; APLLPRE 1:1;
        ACLKCON1 = 0x101;
        APLLFBD1 = 0x96;
        APLLDIV1 = 0x41;        // APOST1DIV 1:4; APOST2DIV 1:1; AVCODIV FVCO/4;
        // CANCLKEN disabled; CANCLKSEL No Clock Selected; CANCLKDIV Divide by 1;
        CANCLKCON = 0x00;
        // ROEN disabled; ROSLP disabled; ROSEL FOSC; ROSIDL disabled; ROSWEN disabled; ROOUT disabled;
        REFOCONL = 0x00;
        // RODIV 0;
        REFOCONH = 0x00;
        // IOLOCK disabled;
        RPCON = 0x00;
        // PMDLOCK disabled;
        PMDCON = 0x00;
        // ADC1MD enabled; T1MD enabled; U2MD enabled; U1MD enabled; SPI2MD enabled; SPI1MD enabled; QEIMD enabled; C1MD enabled; PWMMD enabled; I2C1MD enabled;
        PMD1 = 0x00;
        // CCP2MD enabled; CCP1MD enabled; CCP4MD enabled; CCP3MD enabled; CCP7MD enabled; CCP8MD enabled; CCP5MD enabled; CCP6MD enabled; CCP9MD enabled;
        PMD2 = 0x00;
        // I2C3MD enabled; U3MD enabled; QEI2MD enabled; CRCMD enabled; I2C2MD enabled;
        PMD3 = 0x00;
        // REFOMD enabled;
        PMD4 = 0x00;
        // DMA1MD enabled; SPI3MD enabled; DMA2MD enabled; DMA3MD enabled; DMA0MD enabled;
        PMD6 = 0x00;
        // CMP3MD enabled; PTGMD enabled; CMP1MD enabled; CMP2MD enabled;
        PMD7 = 0x00;
        // DMTMD enabled; CLC3MD enabled; OPAMPMD enabled; BIASMD enabled; CLC4MD enabled; SENT2MD enabled; SENT1MD enabled; CLC1MD enabled; CLC2MD enabled;
        PMD8 = 0x00;
        // CF no clock failure; NOSC FRCPLL; CLKLOCK unlocked; OSWEN Switch is Complete;
        __builtin_write_OSCCONH((uint8_t) ((0x100 >> _OSCCON_NOSC_POSITION) & 0x00FF));
        __builtin_write_OSCCONL((uint8_t) ((0x100 | _OSCCON_OSWEN_MASK) & 0xFF));
        // Wait for Clock switch to occur
        while (OSCCONbits.OSWEN != 0);
        while (OSCCONbits.LOCK != 1);
        
    }

    int main(void)
    {
        WDTCONLbits.ON =0;  //disabled wdt
        ConfigureOscillator();    //init
        
        //other configuration
        _TRISB15 = 0; _TRISC15 = 0; _TRISC0 = 0; _TRISC2 = 0;       //ENA = out
        _TRISC12 = 0; _TRISD15 = 0; _TRISA1 = 0;  _TRISC1 = 0;      //DIR = in
        _TRISB14 = 0; _TRISC14 = 0; _TRISD13 = 0; _TRISD12 = 0;     //STEP = out
        _TRISC13 = 1;_TRISA2 = 1;_TRISC6 = 1;          //error = in
        _CNPUC13 = 1;_CNPUA2 = 1;_CNPUC6 = 1;          //enabled pull up for error  input
        _CMP1MD=1;   //disabled comparator functionality
        _CMP2MD=1;
        _CMP3MD=1;
        _RC15=1;
        _RB15=1;
        _RC0=1;
        _RC2=1;

        //wanted config
        _TRISD14 = 1;
        _CNPUD14 = 1;
        CNCONDbits.CNSTYLE=1;
        CNCONDbits.ON=1;
        CNEN1Dbits.CNEN1D14=1;
        CNEN0Dbits.CNEN0D14=1;
        CNFD=0;             //clear change notification
        _CNDIP=7;       // priority
        IFS1bits.CNCIF = 0;    // Reset change notice interrupt flag
        IEC1bits.CNCIE = 1;     // Enable CN interrupts
        INTCON2bits.GIE = 1;
        
        while(1)
        {
            Nop();
            Nop();
        }
        return 0;
    }

    void __attribute__((__interrupt__,no_auto_psv)) _CNCInterrupt(void)       //interrupt
    {
        if(CNFDbits.CNFD14)
        {
            CNFDbits.CNFD14=0;
        }  
        IFS1bits.CNCIF = 0;      // Clear CN interrupt
    }
    #3
    GregA
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    Re: CN interrupt on dsPIC33CK 2020/09/30 01:10:46 (permalink)
    0
    Hello,
    I have the solution:
    The CN enabled interrupt is by port name:
    IFS1bits.CNCIF is for PORTC, for me: IFS4bits.CNDIF , and for enable: IEC4bits.CNDIF
    And interrupt name is _CNDInterrupt(void)
     
    But in datasheet DS70005349H , we have error, page 126
    CNEN0x: CHANGE NOTIFICATION INTERRUPT ENABLE FOR PORTx REGISTER
    and page 129 CNEN0x bit: Detects a positive transition (from ‘0’ to ‘1’)
    And no information about CNxIF and CNxIE
     
    Thanks
    #4
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