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Shocker
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2020/09/26 06:58:58 (permalink)
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Will a longer acquisition time give a more stable result?

Hi,
 
Based on the datasheet, let's say i calculate the minimum acquisition time is 2us. I believe the acquisition time is the time required to charge the internal capacitance and parasitics.
 
If i take samples with an acquisition time of 3us, 9us, and 12us on a flat DC signal should i expect the results to become more stable or once the minimum acquisition time + a small margin is satisfied the results will not be any more stable?
 
I'm curious because in 8bit sampling (i'm already omitting bit 0 and 1 on the 10bit ADC due to bit flipping), i'm seeing bit 2 also bit flip on a flat DC signal that measures on a silly scope to be far more stable than what the ADC indicates. I'm wondering how i can negate it or if it's just the nature of the system and i have to deal with it.
 
- I've already switched Vref from VCC to the internal 4.096V.
- The PSU unit is from a reputable brand and we regulate it's output with a LM7805 to 5V. The oscilloscope (reputable brand and 50MHz bandwidth) shows the supply is stable. It's also only powering my small 10-15 component board - so there is no other load causing disturbances.
- There are decoupling capacitors on the input, LM7805, the PIC, and op-amps.
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    ric
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 07:30:22 (permalink)
    +1 (1)
    It doesn't matter how many bits you omit, you can always expect to see noise on the lowest bit you use.
     

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    Mysil
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 08:22:52 (permalink)
    +2 (2)
    Hi,
    Depending on board layout, wiring and shielding,
    there will always be several possibilities to pick up noise from outside and inside the microcontroller.
    Examples are 50 or 60 Hz mains hum may be picked up by wiring loops,  or from power supply lines,
    and digital noise from the microcontroller clock and digital circuits. There may be other sources around.
     
    If there are op-amps in the analog circuits, then any noise will be amplified at least as much as the wanted signal.
     
    You have a good oscilloscope, so may switch to AC signal display,
    and increase voltage gain to study noise voltages in various part of circuit.
     
    A trick that have been used, is to set the PIC into Sleep mode immediately after ADC conversion is started,
    and let ADC interrupt signal wake it up when conversion is completed.
    This will reduce noise from digital switching inside the microcontroller.
     
    You may program your microcontroller to calculate max value, min value and average value of multiple ADC measurements.
     
        Mysil
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    Shocker
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 08:37:00 (permalink)
    +1 (1)
    ric
    It doesn't matter how many bits you omit, you can always expect to see noise on the lowest bit you use.


    I don't disagree but shouldn't the immunity to bit flipping be increased since 0.5lsb increases?
     
    0.5 lsb in 10 bit is 2mV.
    0.5 lsb in 8 bit is 8mV.
     
    Mysil
    A trick that have been used, is to set the PIC into Sleep mode immediately after ADC conversion is started,
    and let ADC interrupt signal wake it up when conversion is completed.
    This will reduce noise from digital switching inside the microcontroller.

     
    All good points.
     
    Interesting technique. I'll give it a try.


    So to answer my question, extending the acquistion time won't improve the result?
    #4
    vexorg
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 08:41:25 (permalink)
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    For 8 bit then it should be stable for a pure DC signal, you may get the lowest bit toggling if you are on the boundary point between levels.
     
    If you ref is 4.096v,then 8bit is 16mv per bit, so if on an exact multiple og 16mV then it'll go either way. As in 128mV may give 0x08 or 0x07.
     
    For a stable signal you can use averaging, but for a randomly changing then you'll need to live with the single shot accuracy.
     
    That said, there must be something up with your setup if you cant get a stable 10bit result, 4mV is quite generous per bit for noise.
    post edited by vexorg - 2020/09/27 03:18:02
    #5
    Antipodean
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 09:48:07 (permalink)
    +1 (1)
    Shocker
    ric
    It doesn't matter how many bits you omit, you can always expect to see noise on the lowest bit you use.

    I don't disagree but shouldn't the immunity to bit flipping be increased since 0.5lsb increases?
    0.5 lsb in 10 bit is 2mV.
    0.5 lsb in 8 bit is 8mV.
    ...
    So to answer my question, extending the acquistion time won't improve the result?



    Well, that depends on the exact input voltage. If you are attempting to measure a voltage close to where bit 2 will change state, then yes, you will see exactly what you are seeing.
     
    I have seen ADC outputs flip between binary 10000000 and 01111111 because the input voltage was right on the transition point. When at that point you only need 1 LSB of noise to flip between the states.
    Think about it. If in doubt then get a precision voltage source and slowly work your way up the ADC increments.
     
     

    Do not use my alias in your message body when replying, your message will disappear ...

    Alan
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    1and0
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 09:57:47 (permalink)
    +1 (1)
    Shocker
    I'm curious because in 8bit sampling (i'm already omitting bit 0 and 1 on the 10bit ADC due to bit flipping), i'm seeing bit 2 also bit flip on a flat DC signal that measures on a silly scope to be far more stable than what the ADC indicates. I'm wondering how i can negate it or if it's just the nature of the system and i have to deal with it.

    As others have explained, it will flip when your input voltage is at the transition point. Fixes can be averaging and/or hysteresis.
     
    #7
    NKurzman
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 14:14:46 (permalink)
    +1 (1)
    once you are past the needed acquisition time, then yes the improvement will stop.
    the Details of you input circuit can make it take longer than the data sheet.
    the toggling of the lowest bit between two levels is called "dithering".
     
    #8
    PStechPaul
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 14:23:40 (permalink)
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    If you are driving the ADC input directly from an op-amp, the sampling capacitor should charge up very quickly, whereas it may take longer if you use an R-C input filter. But with an external capacitor of sufficient size, the dynamic impedance will also be low enough to be accurate. You may be able to achieve an additional bit of accuracy and stability by adding a few mV of AC noise, and taking an average of several readings. This is "dithering", and if the signal is very close to the transition point, it will result in a more stable and accurate reading.
     
    https://www.analog.com/en/analog-dialogue/articles/adc-input-noise.html
     
    https://davidswiston.blogspot.com/2014/11/adcs-dithering-when-adding-noise-is.html
     
    Another point, which I encountered recently, can happen if you are scanning several ADC channels, and the signals are very different, or one is a steady DC while the other is rapidly changing. If there is insufficient time between samples, the sampling capacitor must change its voltage level quite a lot, and remnants of the previous measurement may be injected into the new measurement. I solved this by using an ADC interrupt to read a previous conversion and then select the next channel, and a timer interrupt to start the next conversion of the already selected channel. 

     
    #9
    LdB_ECM
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 19:24:28 (permalink)
    +2 (2)
    The easiest solution has always been to go higher ADC bit resolution than required and throw the lowest bit as per comments above noted the jitter on the last digit is unavoidable without circuitry or code complexity.
    If you need 8 bit resolution the use a 9 or 10 bit ADC.
    post edited by LdB_ECM - 2020/09/26 19:39:37
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    ric
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    Re: Will a longer acquisition time give a more stable result? 2020/09/26 19:50:10 (permalink)
    +2 (2)
    As you note, it doesn't matter how many bits you actualy measure, it's impossible to avoid jitter on the lowest bit used.
    Any DC voltage close to the threshold can cause the lowest bit to change with only a tiny amount of noise.
     

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