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Hot!dsPIC33CH Discontinuity in DMA Transfer from ADC

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joey5398
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2020/09/24 13:34:35 (permalink)
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dsPIC33CH Discontinuity in DMA Transfer from ADC

Hey all,
 
I'm using the DMA on a dsPIC33CH to transfer ADC samples to a buffer. The DMA is setup in repeated one-shot mode, and I am feeding in a test sinusoid. I'm running into a problem where there is a discontinuity in the destination buffer. I attached a picture to give an idea of what is happening. This occurs even when I shut off all other processing code, including the DMA interrupt. The only thing happening is the sampling and DMA movement. My initial thought was maybe there is some overhead in the DMA reloading pointers, but then wouldn't the discontinuity always happen at the very beginning of the buffer, or at least in the same spot each time? Currently, the discontinuity does not occur at the same place in the buffer from run to run. In the picture for example, the discontinuity occurs between samples 79 and 85, but in other runs it occurs elsewhere.
 
Anyone have an idea of why this may be happening? I know there is errata with ADC triggers on the DMA (which I have the work around in place for), could it be remnants of that?
 
Link for picture - https://www.dropbox.com/s...discontinuity.jpg?dl=0
 
Thank you!
#1

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    du00000001
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/24 16:25:56 (permalink)
    4 (1)
    Are you reading the buffer while the DMA is active?
    This very much looks so. And the discontinuity would indicate the current write position.
    As your buffer's length is not a multiple of the sine's period, such a discontinuity MUST be present during updating.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #2
    joey5398
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 12:47:15 (permalink)
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    du00000001
    Are you reading the buffer while the DMA is active?
    This very much looks so. And the discontinuity would indicate the current write position.
    As your buffer's length is not a multiple of the sine's period, such a discontinuity MUST be present during updating.


    Just had a total duh moment. Was being inconsistent in how I was halting execution to read the buffer. Of course the discontinuity will be there, it's in the process of overwriting. I have to be able to capture varying frequencies within some passband, so having the buffer length a multiple of the period won't always work. This has been a hefty project, can you tell I'm fried? lol 
    Thanks for the response!
     
    Next challenge is to get processing working on a ping pong setup, as I have to filter this buffer. The hardware setup is working great with the HALFEN interrupt and a double length buffer (data all being moved correctly, interrupting correctly, etc.). For some reason though, the DSP library has no problem with me calling FIR like this:
     
    FIR(BUFFER_SIZE, (fractional*) &filtered_raw_input, (fractional*) &raw_input, &Configurator_BPFFilter);
     
    where the buffers are the same size, but gives me bad results with this: 
     
    if(DMAINT1bits.HALFIF){
        FIR(BUFFER_SIZE, (fractional*) &filtered_raw_input, (fractional*) &raw_input, &Configurator_BPFFilter);
        DMAINT1bits.HALFIF = 0;
    }
    else{
        FIR(BUFFER_SIZE, (fractional*) &filtered_raw_input, (fractional*) &raw_input + BUFFER_SIZE, &Configurator_BPFFilter);
    }
     
    Pointer addresses confirmed to be correct by inspecting the working registers during call, and each one executes on the proper interrupt. raw_input looks solid and is 2*BUFFER_SIZE in length, filtered_raw_input is at least still sinusoidal but with varying attenuation from call to call. I am in the passband and filter works perfectly when tested on calls like that of my first line above. Execution time is confirmed to be within the time it takes for the halfway interrupt. Double checked with the stopwatch. 
     
    If you happen to have any insight into what my be causing this, let me know. Maybe I'm missing something dumb again lol.
    #3
    davea
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 14:25:35 (permalink)
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    DMAINT1bits.HALFIF is it cleared at start of DMA transfers 
    maybe    !DMAINT1bits.HALFIF
    a shot in the dark
    post edited by davea - 2020/09/25 14:26:36
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    du00000001
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 14:31:58 (permalink)
    4 (1)
    I suppose it should read FIR(BUFFER_SIZE/2,...) for the split buffer.
    (Assuming BUFFER_SIZE is the number of elements, not the size of the buffers in bytes.)

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #5
    JPortici
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 15:55:14 (permalink)
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    Actually, in the dsPIC33CK i am experiencing a behaviour that could be described as "DMA from time to time doesn't transfer data from the ADC for a brief amount of time"
     
    my sequence is: TMR interrupt enable ADC, adc convert and DMA copy the DATA. after the last acquisition + transfer the DMA interrupt happens and no transfers until the next TMR interrupt
    will be watching this thread.
    disregard, i reread the thread again and it's not related
    post edited by JPortici - 2020/09/25 21:15:56
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    Murton Pike Systems
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 17:11:40 (permalink)
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    My first attempt at DMA with a 32 bit PIC was poor.
    I kept getting lots of data errors.
    It seems you have to declare destination buffer as  coherent as DMA doesnt update the cache.
    unsigned short __attribute__((coherent)) scopebuffercoherent[scopebufferlength];
    #7
    JPortici
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/25 21:13:29 (permalink)
    4.5 (2)
    this is dsPIC33C. despite it's name it's a 16bit platform.
    thankfully it has no caches
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    joey5398
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/28 06:17:00 (permalink)
    4 (1)
    du00000001
    I suppose it should read FIR(BUFFER_SIZE/2,...) for the split buffer.
    (Assuming BUFFER_SIZE is the number of elements, not the size of the buffers in bytes.)


    BUFFER_SIZE here is the number of elements, and as an argument to FIR, is the number of samples to be filtered. It is already half the size of the input buffer (raw_input is currently 2*BUFFER_SIZE in length).
     
    The destination buffer (filtered_raw_input) is BUFFER_SIZE in length, and so is updated each time (during the halfway interrupt and the completion interrupt). I guess the next thing I can try is to also ping pong that output buffer.
    #9
    du00000001
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/28 09:50:14 (permalink)
    1 (1)
    Not sure we're talkingabout the same numbers:
    • The "half-way interrupt" occurs after acquiring BUFFER_SIZE samples or after BUFFER_SIZE/2 samples?
    • The FIR() call should be provided with the number of samples acquired.
    • The value of "&raw_input + BUFFER_SIZE" does depend on the type of raw_input (maybe not on all compilers - not sure about that). So you might fall into the pit if raw_input is not a byte (char) type.

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
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    joey5398
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/28 11:13:21 (permalink)
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    du00000001
    Not sure we're talkingabout the same numbers:
    • The "half-way interrupt" occurs after acquiring BUFFER_SIZE samples or after BUFFER_SIZE/2 samples?
    • The FIR() call should be provided with the number of samples acquired.
    • The value of "&raw_input + BUFFER_SIZE" does depend on the type of raw_input (maybe not on all compilers - not sure about that). So you might fall into the pit if raw_input is not a byte (char) type.


    Sorry for the confusion,
     
    The half-way interrupt occurs after acquiring BUFFER_SIZE samples. The DMA count and raw_input are 2*BUFFER_SIZE. So for every interrupt, we have acquired BUFFER_SIZE new samples which is what I'm filtering. 
     
    I was worried about the "&raw_input + BUFFER_SIZE" as well, and actually originally had it as &raw_input[BUFFER_SIZE] but same result. I've watched the working registers during each call though and the address being passed correctly matches the address of raw_input. For the halfway interrupt it is the base address, and for the completion interrupt it is correctly the address halfway through the buffer.  
    #11
    du00000001
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    Re: dsPIC33CH Discontinuity in DMA Transfer from ADC 2020/09/28 16:33:22 (permalink)
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    So the calculation with .HALFIF set delivers the expected result while the 2nd calculation delivers . . . whatsoever ?

    PEBKAC / EBKAC / POBCAK / PICNIC (eventually see en.wikipedia.org)
    #12
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