• AVR Freaks

AnsweredHot!Question about processor instruction flush when modifying PCL, Pic18f47k42

Author
syoung
New Member
  • Total Posts : 16
  • Reward points : 0
  • Joined: 2020/08/24 05:27:15
  • Location: 0
  • Status: offline
2020/09/24 11:17:29 (permalink)
0

Question about processor instruction flush when modifying PCL, Pic18f47k42

I am using the below to facilitate a jump table for a state machine.
clrf PCLATU, 0
movf _state, 0, 0
movwf PCLATH, 0
clrf PCL, 0
 
The literature on the processor makes it sound like fetching the next instruction is happening while the core is executing the current instruction. Does anyone know if the code above will add an additional cycle due to a flush of whatever instruction follows clrf PCL, 0? I am literally 1 instruction shy of the speed I need and if there is no fetch instruction flushing wasting a cycle then I'm already set.
 
#1
Antipodean
Super Member
  • Total Posts : 1922
  • Reward points : 0
  • Joined: 2008/12/09 10:19:08
  • Location: Didcot, United Kingdom
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/24 11:53:56 (permalink)
+2 (2)
syoung
I am using the below to facilitate a jump table for a state machine.
clrf PCLATU, 0
movf _state, 0, 0
movwf PCLATH, 0
clrf PCL, 0
 

 
First I don't think that code is going to take you to the table you expect.
 
Second Note 1 under the Instruction Set table will be relevant when you do get the code that works properly.
 

Do not use my alias in your message body when replying, your message will disappear ...

Alan
#2
1and0
Access is Denied
  • Total Posts : 11324
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/24 12:20:22 (permalink) ☼ Best Answerby syoung 2020/09/25 12:23:18
+2 (2)
syoung
I am using the below to facilitate a jump table for a state machine.
clrf PCLATU, 0
movf _state, 0, 0
movwf PCLATH, 0
clrf PCL, 0
 
The literature on the processor makes it sound like fetching the next instruction is happening while the core is executing the current instruction. Does anyone know if the code above will add an additional cycle due to a flush of whatever instruction follows clrf PCL, 0? I am literally 1 instruction shy of the speed I need and if there is no fetch instruction flushing wasting a cycle then I'm already set.

Yes, there will be an extra cycle executed as a NOP when the PC is modified. That being said, do use ",w" for the destination bit and do NOT explicitly code the RAM access bit.
 
Your snippet will take you to your tables at locations of concatenation (0x00 : _state : 0x00).
#3
1and0
Access is Denied
  • Total Posts : 11324
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/24 12:48:44 (permalink) ☄ Helpfulby syoung 2020/09/25 12:11:42
0
syoung
I am literally 1 instruction shy of the speed I need ...

Do you use PCLATU with a different value anywhere else? If not, then that is your one cycle. ;)
 
#4
syoung
New Member
  • Total Posts : 16
  • Reward points : 0
  • Joined: 2020/08/24 05:27:15
  • Location: 0
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/25 12:14:39 (permalink)
0
1and0
syoung
I am using the below to facilitate a jump table for a state machine.
clrf PCLATU, 0
movf _state, 0, 0
movwf PCLATH, 0
clrf PCL, 0
 
The literature on the processor makes it sound like fetching the next instruction is happening while the core is executing the current instruction. Does anyone know if the code above will add an additional cycle due to a flush of whatever instruction follows clrf PCL, 0? I am literally 1 instruction shy of the speed I need and if there is no fetch instruction flushing wasting a cycle then I'm already set.

Yes, there will be an extra cycle executed as a NOP when the PC is modified. That being said, do use ",w" for the destination bit and do NOT explicitly code the RAM access bit.
 
Your snippet will take you to your tables at locations of concatenation (0x00 : _state : 0x00).




I tried not making the access bit explicit but the compiler was adding BANKSEL instructions for vars stored in access locations such as _SQI_state which I have declared with __at(0x0).
#5
1and0
Access is Denied
  • Total Posts : 11324
  • Reward points : 0
  • Joined: 2007/05/06 12:03:20
  • Location: Harry's Gray Matter
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/25 12:41:52 (permalink)
+1 (1)
syoung
I tried not making the access bit explicit but the compiler was adding BANKSEL instructions for vars stored in access locations such as _SQI_state which I have declared with __at(0x0).

Oh, so this is not pure assembly with MPASM. Anyway, look up how to use the __near qualifier in the XC8 User's Guide.
 
#6
syoung
New Member
  • Total Posts : 16
  • Reward points : 0
  • Joined: 2020/08/24 05:27:15
  • Location: 0
  • Status: offline
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/28 04:24:04 (permalink)
0
1and0
syoung
I tried not making the access bit explicit but the compiler was adding BANKSEL instructions for vars stored in access locations such as _SQI_state which I have declared with __at(0x0).

Oh, so this is not pure assembly with MPASM. Anyway, look up how to use the __near qualifier in the XC8 User's Guide.
 


It is almost pure assembly but I wrote it in xc8 using inline asm so that I had access to the debugger without having to re-import the project after every compile. The fact that MPASM doesn't have a debugger is annoying...
#7
ric
Super Member
  • Total Posts : 28660
  • Reward points : 0
  • Joined: 2003/11/07 12:41:26
  • Location: Australia, Melbourne
  • Status: online
Re: Question about processor instruction flush when modifying PCL, Pic18f47k42 2020/09/28 05:53:15 (permalink)
0 (2)
There is a ghost post in this topic.
My guess is that syoung quoted a post by anti-podean without "breaking" his name to avoid the firewall...
 

I also post at: PicForum
Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
NEW USERS: Posting images, links and code - workaround for restrictions.
To get a useful answer, always state which PIC you are using!
#8
Jump to:
© 2020 APG vNext Commercial Version 4.5