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AnsweredHot!PWM Duty Cycle Formula for PIC16

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MicrochipNewbie
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2020/09/18 17:38:09 (permalink)
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PWM Duty Cycle Formula for PIC16

On the specification sheet (e.g. PIC16F87XA), PWM period is specified by (PR2 +1) x 4 x Tosc x (TMR2 Prescale Value).  That all I think I understand - PR2 starts counting from and rolls over on zero hence the PR2+1. Timer2 is driven by the internal oscillator with the default 1/4 divider and prescaler, and so the 4 x Tosc x prescale value.
 
The concept for PWM duty cycle is essentially the same except it resets the S-R flipflop, whereas the PR2/TMR2 comparator sets it for the period, and it's 10 bits vs. 8 bits difference in width.  But the formula given in the specs for PWM Duty Cycle is (CCPR1L:CCP1CON<5:4>) x Tosc x (TMR2 Prescale Value).
  1. Like PWM Period, the PWM Duty Cycle's counter still counts from 0 and rolls over on the next 0. Why is the +1 missing? i.e. shouldn't the first term be (CCPR1L:CCP1CON<5:4> + 1) instead?
  2. TMR2 is driven by Fosc/4. I see nowhere on the specification sheet where it suggests or provides any option to select Fosc instead of Fosc/4 to be the internal source of drive.  Why is the x4 missing here?
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ric
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Re: PWM Duty Cycle Formula for PIC16 2020/09/18 18:31:00 (permalink)
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MicrochipNewbie
Like PWM Period, the PWM Duty Cycle's counter still counts from 0 and rolls over on the next 0. Why is the +1 missing? i.e. shouldn't the first term be (CCPR1L:CCP1CON<5:4> + 1) instead?

There is no "duty cycle counter"
It is a value that is compared with the timer value,and clears the CCPOUT pin when it matches.

TMR2 is driven by Fosc/4. I see nowhere on the specification sheet where it suggests or provides any option to select Fosc instead of Fosc/4 to be the internal source of drive.  Why is the x4 missing here?

Because the hardware cannot do that in a PIC16F87x device.
The fastest that TMR2 can be clocked is Fosc/4.
The CCP module is using the two internal bits inside the prescaler that generates Fosc/4 to match against the CCP1CON<5:4> bits when no extra prescaler is used.
 

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Re: PWM Duty Cycle Formula for PIC16 2020/09/18 18:32:30 (permalink)
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MicrochipNewbieThat all I think I understand - PR2 starts counting from and rolls over on zero hence the [style="line-height: 1.8;"]PR2+1.

 
PR2 doesn't count.  It's value is compared to the Timer.
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Re: PWM Duty Cycle Formula for PIC16 2020/09/18 21:35:43 (permalink)
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I think my question was mistaken or my apology if it wasn't clearly stated.  I understand PR2 or the 10-bit "extended" CCPR1H buffer is a value, not a counter.  The TMR2 increments and compares itself with PR2 or CCPR1H buffer, then sets or resets the flip-flop when either value matches, hence giving the PWM output.  I was questioning the formula [8.3.2] on the specification sheet to be incorrect, or perhaps I'm misunderstanding something.
 
page 67 [8.3.1] PWM Period = [(PR2)+1] x 4 x Tosc x (TMR2 Prescale Value)
page 67 [8.3.2] PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) x Tosc x (TMR2 Prescale Value)
 
  1. Imagine if PR2 is 3, it'll take TMR2 exactly 4x increments to clear the output (0->1, 1->2, 2->3, 3->0). That's what explains the PR2+1 (4) in [8.3.1] instead of just PR2 (3).  The process in [8.3.2] is essentially the same, but the spec sheet left out +1 (i.e. it should be (CCPR1L:CCP1CON<5:4> + 1).  Otherwise, either one of the two formulas has to be incorrect.
  2. I am not following @ric's reply here: "...two internal bits inside the prescaler that generates Fosc/4..."
    Fosc/4 is generated by the internal oscillator and acts as input to the TMR2 prescaler (1:1, 1:4 or 1:16) which configures the speed of TMR2 register incrementation, not the other way around (i.e. your "prescaler generates Fosc/4"). The only explanation I have for the missing x4 multiplication in [8.3.2] is because each 8-bit TMR2 bit incrementation is the 3rd bit of its 10-bit extension (i.e. each 8-bit TMR2 increments is equivalent to an increment of 4 (B'100') for the 10-bit TMR2).  Hence the 4x is canceled out and left with just Tosc instead of Tosc x 4 as in [8.3.1].  
Is that right, or am I getting it all wrong?
post edited by MicrochipNewbie - 2020/09/18 21:45:52
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Re: PWM Duty Cycle Formula for PIC16 2020/09/18 21:52:29 (permalink)
+1 (1)
MicrochipNewbie
Imagine if PR2 is 3, it'll take TMR2 exactly 4x increments to clear the output (0->1, 1->2, 2->3, 3->0). That's what explains the PR2+1 in 8.3.1 instead of just having PR2.  

This is correct.
It means the actual range is 1-256
 

The process in [8.3.2] is essentially the same, but the spec sheet has the +1 missing (i.e. it should be (CCPR1L:CCP1CON<5:4> + 1).  So either one of the two formula has to be incorrect.

This is incorrect.
If CCPRL1 is 1 (and the CCP1CON<5:4> bits are both low), the CCP output will go high when TMR2=0
and will go low immediately when TMR2=1, so it is only high for 1 complete TMR2 cycle.
So, there is no extra "+1" in the calculation.
Setting the CCP1CON<5:4> lets you extend it by another three quarter clocks.

I am not following @ric's reply here: "...two internal bits inside the prescaler that generates Fosc/4..."

Have a look at "FIGURE 8-3:SIMPLIFIED PWM BLOCK DIAGRAM" in the datasheet, particularly "Note 1".
When you are using the TMR2 prescaler, the two most significant bits of the prescaler count are compared with CCP1CON<5:4>
When you are NOT using the TMR2 prescaler (i.e. prescaler = 1:1), then those two bits come from the "prescaler that generates Fosc/4" for the whole PIC.
That is what "Note 1" is saying, and exactly what I said.
 
Once you understand Figure 8-3, all the equations make sense.
 
 

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Re: PWM Duty Cycle Formula for PIC16 2020/09/18 22:44:23 (permalink)
+1 (1)
MicrochipNewbie
I think my question was mistaken or my apology if it wasn't clearly stated.  I understand PR2 or the 10-bit "extended" CCPR1H buffer is a value, not a counter.  The TMR2 increments and compares itself with PR2 or CCPR1H buffer, then sets or resets the flip-flop when either value matches, hence giving the PWM output.  I was questioning the formula [8.3.2] on the specification sheet to be incorrect, or perhaps I'm misunderstanding something.
 
page 67 [8.3.1] PWM Period = [(PR2)+1] x 4 x Tosc x (TMR2 Prescale Value)
page 67 [8.3.2] PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) x Tosc x (TMR2 Prescale Value)
 
Is that right, or am I getting it all wrong?

PR2 is an 8-bit register so its range is 0 to 255. You cannot have a period of zero. When PR2 = 0 you actually have a period of 1; hence (PR2 + 1).

To simplify explaining, let the TMR2 Prescale Value = 1. TMR2 counts at steps of one instruction cycle (4 * Tosc). The duty cycle counts at steps of one oscillator cycle (Tosc); in other words, the two lower bits CCP1CON<5:4> counts at Tosc. For a match, the 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. This 10-bit value is compared against the 8-bit CCPR1L concatenated with the 2-bit CCP1CON<5:4>.
 
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 00:13:47 (permalink)
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Have a look at "FIGURE 8-3:SIMPLIFIED PWM BLOCK DIAGRAM" in the datasheet, particularly "Note 1".
When you are using the TMR2 prescaler, the two most significant bits of the prescaler count are compared with CCP1CON<5:4>

 
This is exactly where the diagram doesn't make sense to me.  The upper comparator compares the 10-bit CCPR1L:CCP1CON<5:4> with the extended 10-bit TMR2.  If for example, a user defines CCP1CON<5:4> to be 10 (binary), and sets the Prescaler to be 1:1 (or having 2 LSB bits of 00 (binary) concatenated to the free-running 8-bit TMR2), the 10-bit TMR2 (now XXXX.XXXX.00) can NEVER match CCPR1L:CCP1CON<5:4> (or XXXX.XXXX.10), because only the the MSB 8-bits of the 10-bit TMR2 is the free running timer itself that increments or get reset in the hardware. The LSB 2-bit that concatenates to the 8-bit TMR2 to form the 10-bit TMR2 forever stays as 3031 (binary) until user changes the Prescaler in the software.  Even after a period reset, the 10-bit TMR2 just turns out to be 0000.0000.10 - the last two bits are the Prescaler defined by the user and will never be 00 (binary) unless the user sets it to be.
post edited by MicrochipNewbie - 2020/09/19 00:27:04
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 00:25:39 (permalink)
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This is exactly where the diagram doesn't make sense to me.  The upper comparator compares the 10-bit CCPR1L:CCP1CON<5:4> with the extended 10-bit TMR2.  If for example, a user defines CCP1CON<5:4> to be 10 (binary), and sets the Prescaler to be 1:1 (or having 2 LSB bits of 00 (binary) concatenated to the free-running 8-bit TMR2), the 10-bit TMR2 (now XXXX.XXXX.00) can NEVER match CCPR1L:CCP1CON<5:4> (or XXXX.XXXX.10), because only the the MSB 8-bits of the 10-bit TMR2 is the free running timer itself that increments or get reset in the hardware. The LSB 2-bit that concatenates to the 8-bit TMR2 to form the 10-bit TMR2 forever stays as 10 (binary) until user changes the Prescaler in the software. 

In this case, the 8-bit TMR2 concatenated with the 2-bit internal Q clock to form a 10-bit value, that will compare with CCPR1L:CCP1CON<5:4>.
 
<edit> The 2-bit internal Q clock will count 00, 01, 10, 11, 00, 01, 10, 11, and so on, at a rate of Fosc.
 
post edited by 1and0 - 2020/09/19 00:30:14
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 00:38:38 (permalink)
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When the Timer2 Prscaler is 1:1, the two lower bits come from the 2-bit internal Q clock. When the Timer2 Precaler is 1:4 or 1:16, the two lower bits come from the upper two bits of the prescaler counter.
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 00:43:48 (permalink)
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..
 If for example, a user defines CCP1CON<5:4> to be 10 (binary), and sets the Prescaler to be 1:1 (or having 2 LSB bits of 00 (binary) concatenated to the free-running 8-bit TMR2), the 10-bit TMR2 (now XXXX.XXXX.00) can NEVER match CCPR1L:CCP1CON<5:4> (or XXXX.XXXX.10), because only the the MSB 8-bits of the 10-bit TMR2 is the free running timer itself that increments or get reset in the hardware.

Rubbish.
Read Note-1 that I already mentioned. Those bits are NOT always .00
 

The LSB 2-bit that concatenates to the 8-bit TMR2 to form the 10-bit TMR2 forever stays as 3031 (binary) until user changes the Prescaler in the software. 

Where did you read this incorrect information?
 

Even after a period reset, the 10-bit TMR2 just turns out to be 0000.0000.10 - the last two bits are the Prescaler defined by the user and will never be 00 (binary) unless the user sets it to be.

Wrong.
You have totally misread something somewhere.
 

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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 00:51:33 (permalink) ☼ Best Answerby MicrochipNewbie 2020/09/21 00:12:14
+2 (2)
When Timer2 Prescaler is 1:16, the Timer2 counter is a 14-bit concatenation of

    8-bit TMR2 : 4-bit Prescaler : 2-bit Q clock

When Timer2 Prescaler is 1:4, the Timer2 counter is a 12-bit concatenation of

    8-bit TMR2 : 2-bit Prescaler : 2-bit Q clock

When Timer2 Prescaler is 1:1, the Timer2 counter is a 10-bit concatenation of

    8-bit TMR2 : 2-bit Q clock

The upper 10 bits of these concatenations are used to compare against the 10-bit CCPR1L:CCP1CON<5:4>.
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 01:35:47 (permalink)
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The 2-bit internal Q clock will count 00, 01, 10, 11, 00, 01, 10, 11, and so on, at a rate of Fosc

 
My understanding now is that these 2 bits do increment at one Tosc, and setting the Prescaler just initializes these 2 bits to start counting from a specific value. If Prescaler is 10, the 2 bits counts from 10,11,00,01 ... and so on. And by "concatenate", it means the circuit "copies" the Prescaler bits in T2CON (T2CKPS1:T2CKPS0) which stays unchanged as its concatenated copies in the 10-bit TMR2 increments along with the timer.   I wish the Microchip can state it more clearly in Note 1. 
 
 
 
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 01:44:31 (permalink)
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When Timer2 Prescaler is 1:16, the Timer2 counter is a 14-bit concatenation of
    8-bit TMR2 : 4-bit Prescaler : 2-bit Q clock  <--- 4 bit Prescaler ??

When Timer2 Prescaler is 1:4, the Timer2 counter is a 12-bit concatenation of
    8-bit TMR2 : 2-bit Prescaler : 2-bit Q clock

When Timer2 Prescaler is 1:1, the Timer2 counter is a 10-bit concatenation of
    8-bit TMR2 : 2-bit Q clock  <--- 0 bit Prescaler??

 
But Timer2 Clock Prescale Select Bits has only TWO bits (T2CKPS1:T2CKPS0).  00 for 1:1, 01 for 1:4, and 1x for 1:16.  Doesn't the Q-Clock just start counting from the Prescaler values? 
 
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 01:46:50 (permalink)
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The 2-bit internal Q clock will count 00, 01, 10, 11, 00, 01, 10, 11, and so on, at a rate of Fosc

 
My understanding now is that these 2 bits do increment at one Tosc, and setting the Prescaler just initializes these 2 bits to start counting from a specific value.

No.
1and0 gave a good explanation of what those bits do in post#11
You have the wrong end of the stick.
 

If Prescaler is 10, the 2 bits counts from 10,11,00,01 ... and so on.

No

And by "concatenate", it means the circuit "copies" the Prescaler bits in T2CON (T2CKPS1:T2CKPS0) which stays unchanged as its concatenated copies in the 10-bit TMR2 increments along with the timer.  

No.
It means "append".
You keep talking about prescaler bits being copied somewhere, which is nonsense.
Drop your preconceptions and read the documentation again with a clear mind.
 

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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 01:54:12 (permalink)
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MicrochipNewbie

When Timer2 Prescaler is 1:16, the Timer2 counter is a 14-bit concatenation of
   8-bit TMR2 : 4-bit Prescaler : 2-bit Q clock  <--- 4 bit Prescaler ??

When Timer2 Prescaler is 1:4, the Timer2 counter is a 12-bit concatenation of
   8-bit TMR2 : 2-bit Prescaler : 2-bit Q clock

When Timer2 Prescaler is 1:1, the Timer2 counter is a 10-bit concatenation of
   8-bit TMR2 : 2-bit Q clock  <--- 0 bit Prescaler??

 
But Timer2 Clock Prescale Select Bits has only TWO bits (T2CKPS1:T2CKPS0).  00 for 1:1, 01 for 1:4, and 1x for 1:16.  Doesn't the Q-Clock just start counting from the Prescaler values? 

You are confusing the two bits used to select which prescaler mode to use, with the bits inside the prescaler itself.
In 1:4 mode, it is a 2 bit counter.
In 1:16 mode, it is a 4 bit counter.
 
The Q bits are the two bits used in a separate prescaler that converts Fosc into Fosc/4 for the entire PIC.
Those bits are never preset to anything, they continuously clock 00, 01, 10, 11 at the speed of Fosc. When they count from 11 back to 00, Fosc/4 counts once.
There is no way to access those bits directly. The only other use for them is when they are compared against the bottom two bits of the PWM duty cycle when the TMR2 prescaler is in 1:1 mode.
 
post edited by ric - 2020/09/19 02:05:41

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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 05:41:54 (permalink)
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Can someone point me to any documentation that explains what Q-Clock is and how is it generated from the oscillator and the definition of Q-bits? There is no mention on that on the specification sheet or DS33023 Reference Manual. It has always been my "preconception" that Q-Clock is just the internal clock clocking at Fosc and Q1-Q4 are just the number of Fosc cycles, but it seems now that the Q-Clock is also a counter register that increments two bits as Q-bits.  Sorry but I've been goolging and digging through documentation but can't find any relevant information.
post edited by MicrochipNewbie - 2020/09/19 05:46:10
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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 07:35:35 (permalink)
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You won't find it anywhere else.
The ONLY place those internal bits are used for anything is in the PWM module.
Just think if you were designing the internal logic of the PIC, how would you generate a clock which is one quarter of the master clock. With a two bit counter of course.
 

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Re: PWM Duty Cycle Formula for PIC16 2020/09/19 10:01:20 (permalink) ☄ Helpfulby MicrochipNewbie 2020/09/21 00:12:31
+1 (1)
MicrochipNewbie
... always been my "preconception" ...

"Empty your cup..." ;)
  • The Timer2 counter is just a binary counter with the lowest bit clocked from the system oscillator Fosc.
  • The Timer2 prescaler selection configures the width of this binary counter, as I have shown in Post #11; the prescaler select bits are NOT the prescaler counter itself.
  • The upper 10 bits of this binary counter is used to compare against the 10-bit CCPR1L:CCP1CON<5:4>.
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Re: PWM Duty Cycle Formula for PIC16 2020/09/20 23:03:32 (permalink)
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I think I've overthought it then was drown in my matrix of assumptions that were straight out erroneous and it's a hell to get out of.  Shut down myself before rereading the whole PWM section again and I think I've finally understood what the posts are saying. So here to summarize: 
 
If Prescaler is 1:
10-bit Timer = TMR<7:0>:2-Bit-QClock
The 10-bit time base increments per Tosc in time.
 
If Prescaler is 4:
10-bit Timer = TMR<7:0>:Prescaler<1:0>
Since the Prescaler is driven by Fosc/4 (or in time, Tosc*4) and the Prescaler of 4 consists of only 2 bits, the 10-bit timer increments per 4*Tosc in time.
 
If Prescaler is 16:
10-bit Timer = TMR<7:0>:Prescaler<3:2>
Since the Prescaler is driven by Fosc/4 (or in time, Tosc*4) and only the upper 2 bits from the 4-bit Prescaler are attached, the 10-bit timer increments per (4*Tosc)*4 or 16*Tosc in time.
 
Hence the formula:
[8.3.2] PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>) x Tosc x (TMR2 Prescale Value)
 
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Re: PWM Duty Cycle Formula for PIC16 2020/09/20 23:45:00 (permalink)
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I think you've got it.
Go back and have another read of 1and0's post#11, which says the same thing in a nice clear manner.
 

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