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PIC24FJ1024GA610: Enhanced Parallel Master Port (EPMP) signal functionality

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Ross Meredith
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2020/07/26 16:58:54 (permalink)
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PIC24FJ1024GA610: Enhanced Parallel Master Port (EPMP) signal functionality

Hi All,
I am finalising the circuitry for a design using the PIC24FJ1024GA610 (100 pin TQFP package).
The device will have the Enhanced Parallel Master Port (EPMP) activated in 8-bit Master Mode.
I have two questions regarding certain EPMP pin behaviour- any help would be much appreciated.
 
Q1. When operating in 8 bit mode using <PMD0-7>, do the unused upper data signal pins <PMD8-15> become free for other I/O functions?
I have read through the Family Reference Manual Section 42 (Enhanced Parallel Master Port), and there is no clarification on this issue.
(the manual does however mention that unused EPMP address/control signals are available for other I/O functions)
 
Q2. What is the function of the PMPCS1 signal? (present on pin 58 as PMPCS1/SCL2/RA2).
This signal is listed in Table 1-3 of the PIC24FJ1024GA610/GB610 Family datasheet as an output.
There is no other mention of this signal in the datasheet other than the pin allocation tables.
This signal appears to be different to the PMCS1 signal (which is available on pin 18, or shared with PMA<14> on pin 71).
There is no mention of the PMPCS1 signal in Section 42 either.
I wish to use the SCL2 function on pin 58, as well as the PMCS1 chip select on pin 18, but I am concerned about the possible complications of the unknown PMPCS1 function.
 
Can anyone help me with the above questions please?
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