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Hot!Does XC16 deal with Core Silicon Bugs?

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NKurzman
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2020/07/02 22:38:00 (permalink)
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Does XC16 deal with Core Silicon Bugs?

I am working on a Project the Needs a and 80 Pin CPU with CAN Bus.
That filters out most 8 -16 bit PICs.
dsPIC33CH64MP508
dsPIC33CK64MP508
dsPIC33EP64GS808
All seem have CPU instruction Errata.  Does the Compiler deal with insuring the Errata is handled or the OPCODES not used?
I am focusing on the EP and the CK.  The Extra Core in the CH will not help the project.
Any other reasons to choose on over the other?
Both seem to have funky UARTs, but I do not need them.
#1

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    JPortici
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 00:22:28 (permalink)
    3.5 (2)
    almost all the "erratas" on the CPU are more like consequences of how the instructions are implemented.
    For example, the ones on the divisions are DUH, it's a limitation of the algorythm. You either want fast division (but have to check for operand correctness) or a general purpose algorythm
     
    Most if not all in the UART cathegory won't apply to standard UART mode
     
    Read the errata carefully :)
     
    i prefer the CK, the 33EP GS is a bit "clunky" for my taste in the analog blocks. I use the GS only where i need multiple DAC outputs
    the CK besides having a higher max clock has also a number of performance boosts if you start diving into assembly, using multiple contexts and such
     
    EDIT: About the compiler: AFAIK it will use the divide instructions only if it can guarantee that there will be no overflows, so basically all 16bit by 16bit operations. Otherwise, use the provided __builtin
    For the other instructions affected by "erratas" IIRC they are mostly dsp instructions or more exotic istructions that may be used in libraries, RTOS or assembly sections but never by general C constructs
    Erratas about consecutive accesses or sequences that may generate traps, the compiler should work around them automatically
    post edited by JPortici - 2020/07/03 01:13:26
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    NKurzman
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 01:19:21 (permalink)
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    The Hardware eratta I can handle on my own.
    I’m assuming the compiler will handle the rest.
    I just wanted to know if that’s a good assumption.
    In reality this could be a pic18.
    But They don’t make an 80 pin version.
    This is for a safety control so the code is going to be straight C and simple.
    #3
    jtemples
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 01:32:09 (permalink)
    5 (1)
    In reality this could be a pic18. But They don’t make an 80 pin version

     
    There are loads of 80-pin PIC18s.
    #4
    JPortici
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 02:11:50 (permalink)
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    NKurzman
    The Hardware eratta I can handle on my own.
    I’m assuming the compiler will handle the rest.
    I just wanted to know if that’s a good assumption.
    In reality this could be a pic18.
    But They don’t make an 80 pin version.
    This is for a safety control so the code is going to be straight C and simple.



    Yes it's a good assumption
    #5
    ric
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 03:01:29 (permalink)
    5 (1)
    jtemples
    In reality this could be a pic18. But They don’t make an 80 pin version

     
    There are loads of 80-pin PIC18s.

    But not with CANBUS.
    The biggest two are 64 pin.
    I'm curious why it must be 80 pin. Do you need lots of inputs?
    It's easy to generate lots of (slow changing) outputs with an SPI peripheral and some 74HC595 chips.

    I also post at: PicForum
    Links to useful PIC information: http://picforum.ric323.co...opic.php?f=59&t=15
    NEW USERS: Posting images, links and code - workaround for restrictions.
    To get a useful answer, always state which PIC you are using!
    #6
    jtemples
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 09:32:47 (permalink)
    3.5 (2)
    Or an external CAN controller.
    #7
    NKurzman
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 10:13:00 (permalink)
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    It’s a safety rated device.
    The more complexity I add to it, the more work I have to do prove It fails safe.
    Most of the other Errata either doesn’t concern me. Or I can work around.
    It’s kind of shocking that they use the same botched UART with so many families of 16 bit chips.

    Any other opinions on CK versus EP?

    I have the perfect 64 pin chip chosen.
    But people have to add stuff.
    #8
    RISC
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 10:38:31 (permalink)
    5 (1)
    Hi,
    In the XC16 compiler manual table 4-7, the -merrata is explained.
    You can activate it from the project options and the output window will list all avaialble ones by adding : -merrata=list in the XC16 (Global options) window.
    Regards 

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #9
    NorthGuy
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 10:40:39 (permalink)
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    ric
    But not with CANBUS.
    The biggest two are 64 pin.

     
    PIC18F8680 is 80-pin and has CAN. But it's very old ...
     
    #10
    RISC
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 10:47:25 (permalink)
    5 (2)
    Hi,
    If you need to use a dsPIC33 in an application requiring functional safety, you can request safety documents under NDA as explained here : https://www.microchip.com...ters/functional-safety
    dsPIC33CK and CH have new features like ECC flash memory and BIST RAM which will help to relalize more safety functions in the end system.
    Similarly from CAN transceiver viewpoint, some new features help realizing better safety critical systems :
    https://www.microchip.com/design-centers/can/can-and-can-fd-functional-safety
    Regards 
     
     

    For support make sure to check first here : http://microchipdeveloper.com
    There are hundreds of PIC, AVR, SAM...which one do YOU use ?
    #11
    Gort2015
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 12:29:10 (permalink)
    2.33 (3)
    Canibus...!
     
    The UART modules on the CH chips are 100% stable.
    I run two at 1,024Kb/s.
     
    On a breadboard.
     
    A member posted Yesterday that the CK chips
    are on a new revision and there is a new eratta.
     
    post edited by Gort2015 - 2020/07/03 12:32:14

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #12
    NKurzman
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/03 23:30:23 (permalink)
    0
    Is there any risk to ignoring the slave core?
    I don’t need it. And it would just be more code to qualify.
    I actually don’t need the UART.
    I may use it earlier on for some Debugging
    Just one CANBus. Some analog. The rest inputs and outputs.
    Normally I would just ignore a chip with core CPU eratta. I guess once I pick one I will verify that it is handled an XC16 with the FAE.
    #13
    Gort2015
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/04 04:27:00 (permalink)
    2.33 (3)
    No risk, the slave is disabled by default.
     
    It is a powerful chip.
    ECC memory.
     
    How do you write code without UART output?
     
     
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #14
    Gort2015
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/04 04:43:46 (permalink)
    2.33 (3)
    UART now @2048Kb/s to PuTTY.
    (Using fractional divide)
     
    100% stable.
     

    MPLab X playing up, bug in your code? Nevermind, Star Trek:Discovery will be with us soon.
    https://www.youtube.com/watch?v=Iu1qa8N2ID0
    + ST:Continues, "What Ships are Made for", Q's back.
    #15
    NKurzman
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    Re: Does XC16 deal with Core Silicon Bugs? 2020/07/04 07:54:06 (permalink)
    0
    The only communication is CANbus.
    If I use the UART for debugging, The code has to be removed in the final version.
    Otherwise I have to qualify it.
    #16
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